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Merge branch 'test/gdma_fetch_data_in_flash' into 'master'

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test(gdma): can read data from flash rodata

See merge request espressif/esp-idf!30479
This commit is contained in:
morris
2024-05-07 12:23:45 +08:00
parent 498cf723f0 2352f17e63
commit 797ce920a7
11 changed files with 64 additions and 17 deletions
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28
components/esp_hw_support/test_apps/dma/main/test_gdma_crc.c
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@@ -11,6 +11,7 @@
#include "freertos/semphr.h"
#include "unity.h"
#include "esp_heap_caps.h"
#include "esp_memory_utils.h"
#include "esp_private/gdma.h"
#include "hal/dma_types.h"
#include "soc/soc_caps.h"
@@ -62,6 +63,8 @@ static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_nu
uint32_t crc_result = 0;
const char *test_input_string = "Share::Connect::Innovate";
size_t input_data_size = strlen(test_input_string);
// this test case also test the GDMA can fetch data from MSPI Flash
TEST_ASSERT_TRUE(esp_ptr_in_drom(test_input_string));
printf("Calculate CRC value for string: \"%s\"\r\n", test_input_string);
gdma_trigger_t m2m_trigger = GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_M2M, 0);
@@ -71,27 +74,22 @@ static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_nu
m2m_trigger.instance_id = __builtin_ctz(free_m2m_id_mask);
TEST_ESP_OK(gdma_connect(tx_chan, m2m_trigger));
// allocate the source and destination buffer from SRAM
// |--------------------------------------------------|
// | 128 bytes DMA descriptor | 128 bytes data buffer |
// |--------------------------------------------------|
size_t sram_alignment = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
uint8_t *src_buf = heap_caps_aligned_calloc(sram_alignment, 1, 256, MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(src_buf);
dma_descriptor_align8_t *tx_descs = (dma_descriptor_align8_t *) src_buf;
uint8_t *src_data = src_buf + 64;
memcpy(src_data, test_input_string, input_data_size);
size_t sram_cache_line_size = cache_hal_get_cache_line_size(CACHE_LL_LEVEL_INT_MEM, CACHE_TYPE_DATA);
size_t alignment = MAX(sram_cache_line_size, 8);
dma_descriptor_align8_t *tx_descs = heap_caps_aligned_calloc(alignment, 1, sizeof(dma_descriptor_align8_t),
MALLOC_CAP_DMA | MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
TEST_ASSERT_NOT_NULL(tx_descs);
tx_descs->buffer = src_data;
tx_descs->dw0.size = 256 - 64;
tx_descs->buffer = (void *)test_input_string;
tx_descs->dw0.size = input_data_size + 1; // +1 for '\0'
tx_descs->dw0.length = input_data_size;
tx_descs->dw0.owner = DMA_DESCRIPTOR_BUFFER_OWNER_DMA;
tx_descs->dw0.suc_eof = 1;
tx_descs->next = NULL;
if (sram_alignment) {
if (sram_cache_line_size) {
// do write-back for the buffer because it's in the cache
TEST_ESP_OK(esp_cache_msync((void *)src_buf, 256, ESP_CACHE_MSYNC_FLAG_DIR_C2M));
TEST_ESP_OK(esp_cache_msync((void *)tx_descs, sizeof(dma_descriptor_align8_t), ESP_CACHE_MSYNC_FLAG_DIR_C2M | ESP_CACHE_MSYNC_FLAG_UNALIGNED));
}
for (int i = 0; i < test_num_crc_algorithm; i++) {
@@ -111,7 +109,7 @@ static void test_gdma_crc_calculation(gdma_channel_handle_t tx_chan, int test_nu
TEST_ASSERT_EQUAL(crc_test_cases[i].expected_result, crc_result);
}
free(src_buf);
free(tx_descs);
}
TEST_CASE("GDMA CRC Calculation", "[GDMA][CRC]")

12
components/hal/esp32p4/include/hal/ahb_dma_ll.h
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@@ -57,6 +57,18 @@ static inline void ahb_dma_ll_reset_fsm(ahb_dma_dev_t *dev)
dev->misc_conf.ahbm_rst_inter = 0;
}
/**
* @brief Preset valid memory range for AHB-DMA
*
* @param dev DMA register base address
*/
static inline void ahb_dma_ll_set_default_memory_range(ahb_dma_dev_t *dev)
{
// AHB-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
dev->intr_mem_start_addr.val = 0x40000000;
dev->intr_mem_end_addr.val = 0x4FFC0000;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word

14
components/hal/esp32p4/include/hal/axi_dma_ll.h
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@@ -59,6 +59,20 @@ static inline void axi_dma_ll_reset_fsm(axi_dma_dev_t *dev)
dev->misc_conf.axim_rst_wr_inter = 0;
}
/**
* @brief Preset valid memory range for AXI-DMA
*
* @param dev DMA register base address
*/
static inline void axi_dma_ll_set_default_memory_range(axi_dma_dev_t *dev)
{
// AXI-DMA can access L2MEM, L2ROM, MSPI Flash, MSPI PSRAM
dev->intr_mem_start_addr.val = 0x4FC00000;
dev->intr_mem_end_addr.val = 0x4FFC0000;
dev->extr_mem_start_addr.val = 0x40000000;
dev->extr_mem_end_addr.val = 0x4C000000;
}
///////////////////////////////////// RX /////////////////////////////////////////
/**
* @brief Get DMA RX channel interrupt status word

1
components/hal/gdma_hal_ahb_v2.c
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@@ -246,4 +246,5 @@ void gdma_ahb_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if SOC_GDMA_SUPPORT_ETM
hal->enable_etm_task = gdma_ahb_hal_enable_etm_task;
#endif // SOC_GDMA_SUPPORT_ETM
ahb_dma_ll_set_default_memory_range(hal->ahb_dma_dev);
}

1
components/hal/gdma_hal_axi.c
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@@ -246,4 +246,5 @@ void gdma_axi_hal_init(gdma_hal_context_t *hal, const gdma_hal_config_t *config)
#if SOC_GDMA_SUPPORT_ETM
hal->enable_etm_task = gdma_axi_hal_enable_etm_task;
#endif // SOC_GDMA_SUPPORT_ETM
axi_dma_ll_set_default_memory_range(hal->axi_dma_dev);
}

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -451,6 +451,10 @@ config SOC_DS_KEY_CHECK_MAX_WAIT_US
int
default 1100
config SOC_DMA_CAN_ACCESS_MSPI_MEM
bool
default y
config SOC_AHB_GDMA_VERSION
int
default 2

3
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -182,6 +182,9 @@
See TRM DS chapter for more details */
#define SOC_DS_KEY_CHECK_MAX_WAIT_US (1100)
/*-------------------------- DMA Common CAPS ----------------------------------------*/
#define SOC_DMA_CAN_ACCESS_MSPI_MEM 1 /*!< DMA can access MSPI memory (e.g. Flash, PSRAM) */
/*-------------------------- GDMA CAPS -------------------------------------*/
#define SOC_AHB_GDMA_VERSION 2
#define SOC_GDMA_SUPPORT_CRC 1