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soc: descriptive part occupy whole component
This commit is contained in:
Renz Bagaporo
340
components/soc/esp32s3/include/soc/i2c_struct.h
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340
components/soc/esp32s3/include/soc/i2c_struct.h
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// Copyright 2017-2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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typedef volatile struct {
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union {
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struct {
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uint32_t period: 14;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} scl_low_period;
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union {
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struct {
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uint32_t sda_force_out: 1;
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uint32_t scl_force_out: 1;
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uint32_t sample_scl_level: 1;
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uint32_t ack_level: 1;
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uint32_t ms_mode: 1;
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uint32_t trans_start: 1;
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uint32_t tx_lsb_first: 1;
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uint32_t rx_lsb_first: 1;
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uint32_t clk_en: 1;
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uint32_t arbitration_en: 1;
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uint32_t fsm_rst: 1;
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uint32_t ref_always_on: 1;
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uint32_t reserved12: 20;
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};
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uint32_t val;
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} ctr;
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union {
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struct {
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uint32_t ack_rec: 1;
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uint32_t slave_rw: 1;
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uint32_t time_out: 1;
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uint32_t arb_lost: 1;
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uint32_t bus_busy: 1;
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uint32_t slave_addressed: 1;
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uint32_t byte_trans: 1;
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uint32_t reserved7: 1;
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uint32_t rx_fifo_cnt: 6;
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uint32_t reserved14: 4;
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uint32_t tx_fifo_cnt: 6;
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uint32_t scl_main_state_last: 3;
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uint32_t reserved27: 1;
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uint32_t scl_state_last: 3;
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uint32_t reserved31: 1;
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};
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uint32_t val;
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} status_reg;
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union {
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struct {
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uint32_t tout: 24;
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uint32_t time_out_en: 1;
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uint32_t reserved25: 7;
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};
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uint32_t val;
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} timeout;
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union {
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struct {
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uint32_t addr: 15;
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uint32_t reserved15: 16;
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uint32_t en_10bit: 1;
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};
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uint32_t val;
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} slave_addr;
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union {
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struct {
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uint32_t rx_fifo_start_addr: 5;
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uint32_t rx_fifo_end_addr: 5;
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uint32_t tx_fifo_start_addr: 5;
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uint32_t tx_fifo_end_addr: 5;
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uint32_t rx_update: 1;
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uint32_t tx_update: 1;
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uint32_t tx_fifo_init_raddr: 5;
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uint32_t rx_fifo_init_waddr: 5;
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};
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uint32_t val;
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} fifo_st;
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union {
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struct {
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uint32_t rx_fifo_full_thrhd: 5;
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uint32_t tx_fifo_empty_thrhd: 5;
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uint32_t nonfifo_en: 1;
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uint32_t fifo_addr_cfg_en: 1;
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uint32_t rx_fifo_rst: 1;
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uint32_t tx_fifo_rst: 1;
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uint32_t nonfifo_rx_thres: 6;
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uint32_t nonfifo_tx_thres: 6;
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uint32_t reserved26: 6;
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};
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uint32_t val;
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} fifo_conf;
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union {
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struct {
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uint8_t data;
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uint8_t reserved[3];
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};
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uint32_t val;
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} fifo_data;
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union {
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struct {
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uint32_t rx_fifo_full: 1;
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uint32_t tx_fifo_empty: 1;
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uint32_t rx_fifo_ovf: 1;
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uint32_t end_detect: 1;
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uint32_t slave_tran_comp: 1;
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uint32_t arbitration_lost: 1;
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uint32_t master_tran_comp: 1;
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uint32_t trans_complete: 1;
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uint32_t time_out: 1;
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uint32_t trans_start: 1;
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uint32_t ack_err: 1;
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uint32_t rx_rec_full: 1;
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uint32_t tx_send_empty: 1;
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uint32_t scl_st_to: 1;
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uint32_t scl_main_st_to: 1;
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uint32_t det_start: 1;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} int_raw;
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union {
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struct {
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uint32_t rx_fifo_full: 1;
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uint32_t tx_fifo_empty: 1;
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uint32_t rx_fifo_ovf: 1;
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uint32_t end_detect: 1;
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uint32_t slave_tran_comp: 1;
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uint32_t arbitration_lost: 1;
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uint32_t master_tran_comp: 1;
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uint32_t trans_complete: 1;
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uint32_t time_out: 1;
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uint32_t trans_start: 1;
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uint32_t ack_err: 1;
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uint32_t rx_rec_full: 1;
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uint32_t tx_send_empty: 1;
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uint32_t scl_st_to: 1;
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uint32_t scl_main_st_to: 1;
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uint32_t det_start: 1;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} int_clr;
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union {
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struct {
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uint32_t rx_fifo_full: 1;
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uint32_t tx_fifo_empty: 1;
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uint32_t rx_fifo_ovf: 1;
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uint32_t end_detect: 1;
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uint32_t slave_tran_comp: 1;
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uint32_t arbitration_lost: 1;
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uint32_t master_tran_comp: 1;
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uint32_t trans_complete: 1;
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uint32_t time_out: 1;
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uint32_t trans_start: 1;
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uint32_t ack_err: 1;
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uint32_t rx_rec_full: 1;
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uint32_t tx_send_empty: 1;
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uint32_t scl_st_to: 1;
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uint32_t scl_main_st_to: 1;
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uint32_t det_start: 1;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} int_ena;
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union {
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struct {
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uint32_t rx_fifo_full: 1;
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uint32_t tx_fifo_empty: 1;
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uint32_t rx_fifo_ovf: 1;
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uint32_t end_detect: 1;
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uint32_t slave_tran_comp: 1;
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uint32_t arbitration_lost: 1;
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uint32_t master_tran_comp: 1;
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uint32_t trans_complete: 1;
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uint32_t time_out: 1;
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uint32_t trans_start: 1;
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uint32_t ack_err: 1;
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uint32_t rx_rec_full: 1;
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uint32_t tx_send_empty: 1;
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uint32_t scl_st_to: 1;
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uint32_t scl_main_st_to: 1;
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uint32_t det_start: 1;
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uint32_t reserved16: 16;
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};
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uint32_t val;
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} int_status;
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union {
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struct {
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uint32_t time: 10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} sda_hold;
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union {
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struct {
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uint32_t time: 10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} sda_sample;
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union {
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struct {
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uint32_t period: 14;
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uint32_t scl_wait_high_period: 14;
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uint32_t reserved28: 4;
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};
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uint32_t val;
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} scl_high_period;
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uint32_t reserved_3c;
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union {
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struct {
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uint32_t time: 10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} scl_start_hold;
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union {
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struct {
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uint32_t time: 10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} scl_rstart_setup;
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union {
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struct {
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uint32_t time: 14;
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uint32_t reserved14: 18;
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};
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uint32_t val;
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} scl_stop_hold;
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union {
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struct {
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uint32_t time: 10;
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uint32_t reserved10: 22;
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};
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uint32_t val;
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} scl_stop_setup;
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union {
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struct {
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uint32_t thres: 3;
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uint32_t en: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} scl_filter_cfg;
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union {
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struct {
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uint32_t thres: 3;
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uint32_t en: 1;
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uint32_t reserved4: 28;
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};
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uint32_t val;
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} sda_filter_cfg;
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union {
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struct {
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uint32_t byte_num: 8; /*Byte_num represent the number of data need to be send or data need to be received.*/
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uint32_t ack_en: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t ack_exp: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
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uint32_t reserved14: 17;
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uint32_t done: 1;
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};
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uint32_t val;
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} command[16];
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union {
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struct {
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uint32_t scl_st_to: 24;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} scl_st_time_out;
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union {
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struct {
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uint32_t scl_main_st_to: 24;
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uint32_t reserved24: 8;
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};
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uint32_t val;
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} scl_main_st_time_out;
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union {
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struct {
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uint32_t scl_rst_slv_en: 1;
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uint32_t scl_rst_slv_num: 5;
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uint32_t scl_pd_en: 1;
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uint32_t sda_pd_en: 1;
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uint32_t reserved8: 24;
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};
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uint32_t val;
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} scl_sp_conf;
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uint32_t reserved_a4;
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uint32_t reserved_a8;
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uint32_t reserved_ac;
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uint32_t reserved_b0;
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uint32_t reserved_b4;
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uint32_t reserved_b8;
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uint32_t reserved_bc;
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uint32_t reserved_c0;
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uint32_t reserved_c4;
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uint32_t reserved_c8;
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uint32_t reserved_cc;
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uint32_t reserved_d0;
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uint32_t reserved_d4;
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uint32_t reserved_d8;
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uint32_t reserved_dc;
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uint32_t reserved_e0;
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uint32_t reserved_e4;
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uint32_t reserved_e8;
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uint32_t reserved_ec;
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uint32_t reserved_f0;
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uint32_t reserved_f4;
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uint32_t date; /**/
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uint32_t reserved_fc;
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uint32_t ram_data[32]; /**/
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} i2c_dev_t;
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extern i2c_dev_t I2C0;
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extern i2c_dev_t I2C1;
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#ifdef __cplusplus
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}
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#endif
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