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fix(esp_system): hp periph clk should not be gated on core/system reset

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Song Ruo Jing
2024-11-29 21:36:58 +08:00
parent 2deeaece7d
commit 7b852faf66
3 changed files with 37 additions and 26 deletions
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6
components/bootloader_support/src/bootloader_console.c
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@@ -74,6 +74,12 @@ void bootloader_console_init(void)
// Enable the peripheral
uart_ll_enable_bus_clock(uart_num, true);
uart_ll_reset_register(uart_num);
// Set clock source
#if SOC_UART_SUPPORT_XTAL_CLK
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_XTAL);
#else
uart_ll_set_sclk(UART_LL_GET_HW(uart_num), (soc_module_clk_t)UART_SCLK_APB);
#endif
// Reset TX and RX FIFOs
uart_ll_txfifo_rst(UART_LL_GET_HW(uart_num));
uart_ll_rxfifo_rst(UART_LL_GET_HW(uart_num));