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hal: Add initial ESP32-C3 support

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From internal commit 7761d6e8
This commit is contained in:
Angus Gratton
2020-11-26 16:06:21 +11:00
parent b68094199f
commit 7c08be5771
61 changed files with 9842 additions and 71 deletions
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51
components/hal/esp32s3/include/hal/spi_ll.h
View File

@@ -34,17 +34,12 @@
extern "C" {
#endif
/// Registers to reset during initialization. Don't use in app.
#define SPI_LL_CPU_FIFO_RST_MASK (SPI_BUF_AFIFO_RST | SPI_RX_AFIFO_RST)
/// Registers to reset during initialization. Don't use in app.
#define SPI_LL_DMA_FIFO_RST_MASK (SPI_DMA_AFIFO_RST | SPI_RX_AFIFO_RST)
/// Interrupt not used. Don't use in app.
#define SPI_LL_UNUSED_INT_MASK (SPI_TRANS_DONE_INT_ENA | SPI_SLV_WR_DMA_DONE_INT_ENA | SPI_SLV_RD_DMA_DONE_INT_ENA | SPI_SLV_WR_BUF_DONE_INT_ENA | SPI_SLV_RD_BUF_DONE_INT_ENA)
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)data<<(32-len))
/// This is the expected clock frequency
#define SPI_LL_PERIPH_CLK_FREQ (80 * 1000000)
#define SPI_LL_GET_HW(ID) ((ID)==0? ({abort();NULL;}):((ID)==1? &GPSPI2 : &GPSPI3))
/**
@@ -223,25 +218,51 @@ static inline void spi_ll_slave_reset(spi_dev_t *hw)
}
/**
* Reset SPI CPU FIFO
* Reset SPI CPU TX FIFO
*
* On ESP32S3, this function is not seperated
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_cpu_fifo_reset(spi_dev_t *hw)
static inline void spi_ll_cpu_tx_fifo_reset(spi_dev_t *hw)
{
hw->dma_conf.val |= SPI_LL_CPU_FIFO_RST_MASK;
hw->dma_conf.val &= ~SPI_LL_CPU_FIFO_RST_MASK;
hw->dma_conf.buf_afifo_rst = 1;
hw->dma_conf.buf_afifo_rst = 0;
}
/**
* Reset SPI DMA FIFO
* Reset SPI CPU RX FIFO
*
* On ESP32S3, this function is not seperated
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_dma_fifo_reset(spi_dev_t *hw)
static inline void spi_ll_cpu_rx_fifo_reset(spi_dev_t *hw)
{
hw->dma_conf.val |= SPI_LL_DMA_FIFO_RST_MASK;
hw->dma_conf.val &= ~SPI_LL_DMA_FIFO_RST_MASK;
hw->dma_conf.rx_afifo_rst = 1;
hw->dma_conf.rx_afifo_rst = 0;
}
/**
* Reset SPI DMA TX FIFO
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_dma_tx_fifo_reset(spi_dev_t *hw)
{
hw->dma_conf.dma_afifo_rst = 1;
hw->dma_conf.dma_afifo_rst = 0;
}
/**
* Reset SPI DMA RX FIFO
*
* @param hw Beginning address of the peripheral registers.
*/
static inline void spi_ll_dma_rx_fifo_reset(spi_dev_t *hw)
{
hw->dma_conf.rx_afifo_rst = 1;
hw->dma_conf.rx_afifo_rst = 0;
}
/**

4
components/hal/esp32s3/include/hal/systimer_ll.h
View File

@@ -79,13 +79,13 @@ __attribute__((always_inline)) static inline void systimer_ll_apply_counter_valu
/*******************alarm*************************/
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_value(uint32_t alarm_id, uint64_t value)
__attribute__((always_inline)) static inline void systimer_ll_set_alarm_target(uint32_t alarm_id, uint64_t value)
{
REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8, value & 0xFFFFFFFF);
REG_WRITE(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8, (value >> 32) & 0xFFFFF);
}
__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_value(uint32_t alarm_id)
__attribute__((always_inline)) static inline uint64_t systimer_ll_get_alarm_target(uint32_t alarm_id)
{
return ((uint64_t) REG_READ(SYS_TIMER_SYSTIMER_TARGET0_HI_REG + alarm_id * 8) << 32) \
| REG_READ(SYS_TIMER_SYSTIMER_TARGET0_LO_REG + alarm_id * 8);