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Merge branch 'esp32c5/add_adc_support' into 'master'

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ADC: bringup ADC oneshot and continuous mode on C5

Closes IDF-8701 and IDF-8703

See merge request espressif/esp-idf!31940
This commit is contained in:
Gao Xu
2024-07-17 16:46:52 +08:00
parent 2afbcd1bb4 2f49a2e9c8
commit 7d3ac1abe4
29 changed files with 1055 additions and 62 deletions
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20
components/soc/esp32c5/adc_periph.c Normal file
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@@ -0,0 +1,20 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "soc/adc_periph.h"
/* Store IO number corresponding to the ADC channel number. */
const int adc_channel_io_map[SOC_ADC_PERIPH_NUM][SOC_ADC_MAX_CHANNEL_NUM] = {
/* ADC1 */
{
ADC1_CHANNEL_0_GPIO_NUM,
ADC1_CHANNEL_1_GPIO_NUM,
ADC1_CHANNEL_2_GPIO_NUM,
ADC1_CHANNEL_3_GPIO_NUM,
ADC1_CHANNEL_4_GPIO_NUM,
ADC1_CHANNEL_5_GPIO_NUM,
},
};

78
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
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@@ -3,6 +3,10 @@
# using gen_soc_caps_kconfig.py, do not edit manually
#####################################################
config SOC_ADC_SUPPORTED
bool
default y
config SOC_UART_SUPPORTED
bool
default y
@@ -207,13 +211,85 @@ config SOC_AES_SUPPORT_AES_256
bool
default y
config SOC_ADC_DIG_CTRL_SUPPORTED
bool
default y
config SOC_ADC_DIG_IIR_FILTER_SUPPORTED
bool
default y
config SOC_ADC_MONITOR_SUPPORTED
bool
default y
config SOC_ADC_DMA_SUPPORTED
bool
default y
config SOC_ADC_PERIPH_NUM
int
default 1
config SOC_ADC_MAX_CHANNEL_NUM
int
default 7
default 6
config SOC_ADC_ATTEN_NUM
int
default 4
config SOC_ADC_DIGI_CONTROLLER_NUM
int
default 1
config SOC_ADC_PATT_LEN_MAX
int
default 8
config SOC_ADC_DIGI_MAX_BITWIDTH
int
default 12
config SOC_ADC_DIGI_MIN_BITWIDTH
int
default 12
config SOC_ADC_DIGI_IIR_FILTER_NUM
int
default 2
config SOC_ADC_DIGI_MONITOR_NUM
int
default 2
config SOC_ADC_DIGI_RESULT_BYTES
int
default 4
config SOC_ADC_DIGI_DATA_BYTES_PER_CONV
int
default 4
config SOC_ADC_SAMPLE_FREQ_THRES_HIGH
int
default 83333
config SOC_ADC_SAMPLE_FREQ_THRES_LOW
int
default 611
config SOC_ADC_RTC_MIN_BITWIDTH
int
default 12
config SOC_ADC_RTC_MAX_BITWIDTH
int
default 12
config SOC_ADC_SHARED_POWER
bool
default y
config SOC_SHARED_IDCACHE_SUPPORTED
bool

28
components/soc/esp32c5/include/soc/adc_channel.h
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@@ -6,24 +6,20 @@
#pragma once
// TODO: [ESP32-C5] IDF-8701 Check the channel
#define ADC1_GPIO0_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 0
#define ADC1_GPIO1_CHANNEL 0
#define ADC1_CHANNEL_0_GPIO_NUM 1
#define ADC1_GPIO1_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 1
#define ADC1_GPIO2_CHANNEL 1
#define ADC1_CHANNEL_1_GPIO_NUM 2
#define ADC1_GPIO2_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 2
#define ADC1_GPIO3_CHANNEL 2
#define ADC1_CHANNEL_2_GPIO_NUM 3
#define ADC1_GPIO3_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 3
#define ADC1_GPIO4_CHANNEL 3
#define ADC1_CHANNEL_3_GPIO_NUM 4
#define ADC1_GPIO4_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 4
#define ADC1_GPIO5_CHANNEL 4
#define ADC1_CHANNEL_4_GPIO_NUM 5
#define ADC1_GPIO5_CHANNEL 5
#define ADC1_CHANNEL_5_GPIO_NUM 5
#define ADC1_GPIO6_CHANNEL 6
#define ADC1_CHANNEL_6_GPIO_NUM 6
#define ADC1_GPIO6_CHANNEL 5
#define ADC1_CHANNEL_5_GPIO_NUM 6

2
components/soc/esp32c5/include/soc/clk_tree_defs.h
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@@ -433,7 +433,7 @@ typedef enum { // TODO: [ESP32C5] IDF-8691, IDF-8692 (inherit from C6)
/**
* @brief ADC digital controller clock source
*/
typedef enum { // TODO: [ESP32C5] IDF-8701, IDF-8702, IDF-8703 (inherit from C6)
typedef enum {
ADC_DIGI_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the source clock */
ADC_DIGI_CLK_SRC_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the source clock */
ADC_DIGI_CLK_SRC_RC_FAST = SOC_MOD_CLK_RC_FAST, /*!< Select RC_FAST as the source clock */

55
components/soc/esp32c5/include/soc/regi2c_saradc.h Normal file
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@@ -0,0 +1,55 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
/**
* @file regi2c_saradc.h
* @brief Register definitions for analog to calibrate initial code for getting a more precise voltage of SAR ADC.
*
* This file lists register fields of SAR, located on an internal configuration
* bus. These definitions are used via macros defined in regi2c_ctrl.h, by
* function in adc_ll.h.
*/
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB 0x0
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_MSB 0x7
#define I2C_SAR_ADC_SAR1_INIT_CODE_LSB_LSB 0x0
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB 0x1
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_MSB 0x3
#define I2C_SAR_ADC_SAR1_INIT_CODE_MSB_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_SAMPLE_CYCLE_ADDR 0x5
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR2_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 0x3
#define I2C_SARADC_TSENS_DAC_LSB 0x0

46
components/soc/esp32c5/include/soc/soc_caps.h
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@@ -17,7 +17,7 @@
#pragma once
/*-------------------------- COMMON CAPS ---------------------------------------*/
// #define SOC_ADC_SUPPORTED 1 // TODO: [ESP32C5] IDF-8701
#define SOC_ADC_SUPPORTED 1
// #define SOC_DEDICATED_GPIO_SUPPORTED 1 // TODO: [ESP32C5] IDF-8725
#define SOC_UART_SUPPORTED 1
#define SOC_GDMA_SUPPORTED 1
@@ -94,32 +94,32 @@
/*-------------------------- ADC CAPS -------------------------------*/
/*!< SAR ADC Module*/
// #define SOC_ADC_DIG_CTRL_SUPPORTED 1
// #define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
// #define SOC_ADC_MONITOR_SUPPORTED 1
// #define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
// #define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_DIG_CTRL_SUPPORTED 1
#define SOC_ADC_DIG_IIR_FILTER_SUPPORTED 1
#define SOC_ADC_MONITOR_SUPPORTED 1
#define SOC_ADC_DIG_SUPPORTED_UNIT(UNIT) 1 //Digital controller supported ADC unit
#define SOC_ADC_DMA_SUPPORTED 1
#define SOC_ADC_PERIPH_NUM (1U)
// #define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (7)
#define SOC_ADC_MAX_CHANNEL_NUM (7)
// #define SOC_ADC_ATTEN_NUM (4)
#define SOC_ADC_CHANNEL_NUM(PERIPH_NUM) (6)
#define SOC_ADC_MAX_CHANNEL_NUM (6)
#define SOC_ADC_ATTEN_NUM (4)
/*!< Digital */
// #define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
// #define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
// #define SOC_ADC_DIGI_MAX_BITWIDTH (12)
// #define SOC_ADC_DIGI_MIN_BITWIDTH (12)
// #define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
// #define SOC_ADC_DIGI_MONITOR_NUM (2)
// #define SOC_ADC_DIGI_RESULT_BYTES (4)
// #define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
#define SOC_ADC_DIGI_CONTROLLER_NUM (1U)
#define SOC_ADC_PATT_LEN_MAX (8) /*!< Two pattern tables, each contains 4 items. Each item takes 1 byte */
#define SOC_ADC_DIGI_MAX_BITWIDTH (12)
#define SOC_ADC_DIGI_MIN_BITWIDTH (12)
#define SOC_ADC_DIGI_IIR_FILTER_NUM (2)
#define SOC_ADC_DIGI_MONITOR_NUM (2)
#define SOC_ADC_DIGI_RESULT_BYTES (4)
#define SOC_ADC_DIGI_DATA_BYTES_PER_CONV (4)
/*!< F_sample = F_digi_con / 2 / interval. F_digi_con = 5M for now. 30 <= interval <= 4095 */
// #define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
// #define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
#define SOC_ADC_SAMPLE_FREQ_THRES_HIGH 83333
#define SOC_ADC_SAMPLE_FREQ_THRES_LOW 611
/*!< RTC */
// #define SOC_ADC_RTC_MIN_BITWIDTH (12)
// #define SOC_ADC_RTC_MAX_BITWIDTH (12)
#define SOC_ADC_RTC_MIN_BITWIDTH (12)
#define SOC_ADC_RTC_MAX_BITWIDTH (12)
/*!< Calibration */
// #define SOC_ADC_CALIBRATION_V1_SUPPORTED (1) /*!< support HW offset calibration version 1*/
@@ -127,10 +127,10 @@
// #define SOC_ADC_CALIB_CHAN_COMPENS_SUPPORTED (1) /*!< support channel compensation to the HW offset calibration */
/*!< Interrupt */
// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1)
// #define SOC_ADC_TEMPERATURE_SHARE_INTR (1) // TODO: [ESP32C5] IDF-8727
/*!< ADC power control is shared by PWDET */
// #define SOC_ADC_SHARED_POWER 1
#define SOC_ADC_SHARED_POWER 1
// ESP32C5-TODO: Copy from esp32C5, need check
/*-------------------------- APB BACKUP DMA CAPS -------------------------------*/