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Merge branch 'bugfix/timestamp' into 'master'

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fix(global, log): correct the CCOUNT register when switching CPU clock during boot 2nd and before scheduler.

See merge request !1296
This commit is contained in:
Ivan Grokhotkov
2017-09-26 16:15:42 +08:00
parent b7a79ab67e 9d9e771933
commit 7d436c9a44
3 changed files with 23 additions and 2 deletions
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10
components/esp32/clk.c
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@@ -27,6 +27,7 @@
#include "soc/rtc_cntl_reg.h"
#include "soc/dport_reg.h"
#include "soc/i2s_reg.h"
#include "xtensa/core-macros.h"
/* Number of cycles to wait from the 32k XTAL oscillator to consider it running.
* Larger values increase startup delay. Smaller values may cause false positive
@@ -35,6 +36,8 @@
#define XTAL_32K_DETECT_CYCLES 32
#define SLOW_CLK_CAL_CYCLES CONFIG_ESP32_RTC_CLK_CAL_CYCLES
#define MHZ (1000000)
static void select_rtc_slow_clk(rtc_slow_freq_t slow_clk);
static const char* TAG = "clk";
@@ -77,7 +80,14 @@ void esp_clk_init(void)
// Wait for UART TX to finish, otherwise some UART output will be lost
// when switching APB frequency
uart_tx_wait_idle(CONFIG_CONSOLE_UART_NUM);
uint32_t freq_before = rtc_clk_cpu_freq_value(rtc_clk_cpu_freq_get()) / MHZ ;
rtc_clk_cpu_freq_set(freq);
// Re calculate the ccount to make time calculation correct.
uint32_t freq_after = CONFIG_ESP32_DEFAULT_CPU_FREQ_MHZ;
XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
}
void IRAM_ATTR ets_update_cpu_frequency(uint32_t ticks_per_us)