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https://github.com/espressif/esp-idf.git
synced 2025-08-17 15:15:02 +00:00
lcd: allow execlusive use of i80 bus
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@@ -71,6 +71,9 @@ struct esp_lcd_i80_bus_t {
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lcd_i80_trans_descriptor_t *cur_trans; // Current transaction
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lcd_panel_io_i80_t *cur_device; // Current working device
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LIST_HEAD(i80_device_list, lcd_panel_io_i80_t) device_list; // Head of i80 device list
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struct {
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unsigned int exclusive: 1; // Indicate whether the I80 bus is owned by one device (whose CS GPIO is not assigned) exclusively
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} flags;
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dma_descriptor_t dma_nodes[]; // DMA descriptor pool, the descriptors are shared by all i80 devices
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};
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@@ -233,7 +236,17 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p
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{
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esp_err_t ret = ESP_OK;
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lcd_panel_io_i80_t *i80_device = NULL;
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bool bus_exclusive = false;
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ESP_GOTO_ON_FALSE(bus && io_config && ret_io, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
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// check if the bus has been configured as exclusive
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portENTER_CRITICAL(&bus->spinlock);
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if (!bus->flags.exclusive) {
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bus->flags.exclusive = io_config->cs_gpio_num < 0;
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} else {
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bus_exclusive = true;
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}
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portEXIT_CRITICAL(&bus->spinlock);
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ESP_GOTO_ON_FALSE(!bus_exclusive, ESP_ERR_INVALID_STATE, err, TAG, "bus has been exclusively owned by device");
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// because we set the I2S's left channel data same to right channel, so f_pclk = f_i2s/pclk_div/2
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uint32_t pclk_prescale = bus->resolution_hz / 2 / io_config->pclk_hz;
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ESP_GOTO_ON_FALSE(pclk_prescale > 0 && pclk_prescale <= I2S_LL_BCK_MAX_PRESCALE, ESP_ERR_NOT_SUPPORTED, err, TAG,
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@@ -269,10 +282,12 @@ esp_err_t esp_lcd_new_panel_io_i80(esp_lcd_i80_bus_handle_t bus, const esp_lcd_p
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i80_device->base.del = panel_io_i80_del;
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i80_device->base.tx_param = panel_io_i80_tx_param;
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i80_device->base.tx_color = panel_io_i80_tx_color;
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// CS signal is controlled by software
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gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default
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gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_config->cs_gpio_num], PIN_FUNC_GPIO);
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if (io_config->cs_gpio_num >= 0) {
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// CS signal is controlled by software
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gpio_set_level(io_config->cs_gpio_num, !io_config->flags.cs_active_high); // de-assert by default
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gpio_set_direction(io_config->cs_gpio_num, GPIO_MODE_OUTPUT);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[io_config->cs_gpio_num], PIN_FUNC_GPIO);
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}
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*ret_io = &(i80_device->base);
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ESP_LOGD(TAG, "new i80 lcd panel io @%p on bus(%d), pclk=%uHz", i80_device, bus->bus_id, i80_device->pclk_hz);
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return ESP_OK;
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@@ -646,10 +661,12 @@ static void lcd_i80_switch_devices(lcd_panel_io_i80_t *cur_device, lcd_panel_io_
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if (next_device != cur_device) {
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// reconfigure PCLK for the new device
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i2s_ll_tx_set_bck_div_num(bus->hal.dev, next_device->clock_prescale);
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if (cur_device) { // de-assert current device
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if (cur_device && cur_device->cs_gpio_num >= 0) { // de-assert current device
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gpio_set_level(cur_device->cs_gpio_num, !cur_device->flags.cs_active_high);
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}
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gpio_set_level(next_device->cs_gpio_num, next_device->flags.cs_active_high); // select the next device
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if (next_device->cs_gpio_num >= 0) {
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gpio_set_level(next_device->cs_gpio_num, next_device->flags.cs_active_high); // select the next device
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}
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// the WR signal (a.k.a the PCLK) generated by I2S is low level in idle stage
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// but most of 8080 LCDs require the WR line to be in high level during idle stage
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esp_rom_gpio_connect_out_signal(bus->wr_gpio_num, lcd_periph_signals.buses[bus->bus_id].wr_sig, !next_device->flags.pclk_idle_low, false);
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