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Merge branch 'fix/parlio_add_gdma_fifo_reset_v5.4' into 'release/v5.4'

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fix(parlio_tx): add clock and fifo reset in disable function (v5.4)

See merge request espressif/esp-idf!36273
This commit is contained in:
morris
2025-04-03 10:27:04 +08:00
parent ae57289414 da4c0a3a8d
commit 7e1238de97
8 changed files with 202 additions and 41 deletions
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6
components/hal/esp32c5/include/hal/parlio_ll.h
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@@ -385,6 +385,7 @@ static inline void parlio_ll_rx_update_config(parl_io_dev_t *dev)
* @param dev Parallel IO register base address
* @param src Clock source
*/
__attribute__((always_inline))
static inline void parlio_ll_tx_set_clock_source(parl_io_dev_t *dev, parlio_clock_source_t src)
{
(void)dev;
@@ -488,8 +489,11 @@ static inline void parlio_ll_tx_enable_clock_gating(parl_io_dev_t *dev, bool en)
/**
* @brief Start TX unit to transmit data
*
* @note The hardware monitors the rising edge of tx_start as the trigger signal.
* Once the transmission starts, it cannot be stopped by clearing tx_start.
*
* @param dev Parallel IO register base address
* @param en True to start, False to stop
* @param en True to start, False to reset the reg state (not meaning the TX unit will be stopped)
*/
__attribute__((always_inline))
static inline void parlio_ll_tx_start(parl_io_dev_t *dev, bool en)