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Merge branch 'refactor/regi2c_mst_clock_enable' into 'master'
refactor(regi2c): analog i2c mst clock should be enabled/disabled per usage Closes IDF-10492 and IDF-10693 See merge request espressif/esp-idf!32682
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@@ -1031,10 +1031,18 @@ config SOC_CLK_LP_FAST_SUPPORT_XTAL
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bool
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default y
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config SOC_CLK_LP_FAST_SUPPORT_XTAL_D2
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bool
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default y
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config SOC_RCC_IS_INDEPENDENT
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bool
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default y
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config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
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bool
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default y
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config SOC_WIFI_HW_TSF
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bool
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default y
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@@ -89,9 +89,10 @@ typedef enum {
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typedef enum {
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SOC_RTC_FAST_CLK_SRC_RC_FAST = 0, /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_D2 = 1, /*!< Select XTAL_D2_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL_D2` */
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SOC_RTC_FAST_CLK_SRC_XTAL = 2, /*!< Select XTAL_CLK as RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_INVALID, /*!< Invalid RTC_FAST_CLK source */
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SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL_D2, /*!< XTAL_D2_CLK is the default clock source for RTC_FAST_CLK */
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} soc_rtc_fast_clk_src_t;
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/**
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@@ -463,8 +463,12 @@
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#define SOC_CLK_XTAL32K_SUPPORTED (1) /*!< Support to connect an external low frequency crystal */
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#define SOC_CLK_OSC_SLOW_SUPPORTED (1) /*!< Support to connect an external oscillator, not a crystal */
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#define SOC_CLK_LP_FAST_SUPPORT_XTAL (1) /*!< Support XTAL clock as the LP_FAST clock source */
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#define SOC_CLK_LP_FAST_SUPPORT_XTAL_D2 (1) /*!< Support XTAL_D2 clock as the LP_FAST clock source */
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#define SOC_RCC_IS_INDEPENDENT 1 /*!< Reset and Clock Control is independent, thanks to the PCR registers */
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#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE (1) /*!< Any regi2c operation needs enable the analog i2c master clock first */
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/*-------------------------- Temperature Sensor CAPS -------------------------------------*/
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// #define SOC_TEMPERATURE_SENSOR_SUPPORT_FAST_RC (1)
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// #define SOC_TEMPERATURE_SENSOR_SUPPORT_XTAL (1)
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