Merge branch 'refactor/regi2c_mst_clock_enable' into 'master'

refactor(regi2c): analog i2c mst clock should be enabled/disabled per usage

Closes IDF-10492 and IDF-10693

See merge request espressif/esp-idf!32682

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -1935,10 +1935,6 @@ config SOC_CLK_RC_FAST_SUPPORT_CALIBRATION
     bool
     default y
 
-config SOC_MODEM_CLOCK_IS_INDEPENDENT
-    bool
-    default n
-
 config SOC_CLK_APLL_SUPPORTED
     bool
     default y
@@ -1967,6 +1963,10 @@ config SOC_PERIPH_CLK_CTRL_SHARED
     bool
     default y
 
+config SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE
+    bool
+    default y
+
 config SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT
     bool
     default y

components/soc/esp32p4/include/soc/clk_tree_defs.h

@@ -103,9 +103,12 @@ typedef enum {
 typedef enum {
     SOC_RTC_FAST_CLK_SRC_RC_FAST = 0,      /*!< Select RC_FAST_CLK as RTC_FAST_CLK source */
     SOC_RTC_FAST_CLK_SRC_XTAL = 1,         /*!< Select XTAL_CLK as RTC_FAST_CLK source */
-    SOC_RTC_FAST_CLK_SRC_XTAL_DIV = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */
     SOC_RTC_FAST_CLK_SRC_LP_PLL = 2,       /*!< Select LP_PLL_CLK as RTC_FAST_CLK source (LP_PLL_CLK is a 8MHz clock sourced from RC32K or XTAL32K) */
     SOC_RTC_FAST_CLK_SRC_INVALID,          /*!< Invalid RTC_FAST_CLK source */
+
+    SOC_RTC_FAST_CLK_SRC_DEFAULT = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< XTAL_CLK is the default clock source for RTC_FAST_CLK */
+
+    SOC_RTC_FAST_CLK_SRC_XTAL_DIV __attribute__((deprecated)) = SOC_RTC_FAST_CLK_SRC_XTAL, /*!< Alias name for `SOC_RTC_FAST_CLK_SRC_XTAL` */
 } soc_rtc_fast_clk_src_t;
 
 /**
@@ -159,8 +162,8 @@ typedef enum {
     SOC_MOD_CLK_XTAL_D2,                       /*!< XTAL_D2_CLK comes from the external 40MHz crystal, passing a div of 2 to the LP peripherals */
     SOC_MOD_CLK_LP_PLL,                        /*!< LP_PLL is from 32kHz XTAL oscillator frequency multipliers, it has a fixed frequency of 8MHz */
     SOC_MOD_CLK_LP_DYN_FAST,                   /*!< LP_DYN_FAST can be derived from RTC_SLOW_CLK or RTC_FAST_CLK depending on the chip’s power mode:
-                                                    in active mode, select RTC_FAST_CLK as the clock source;
-                                                    in light/deep sleep mode, select RTC_SLOW_CLK as the clock source */
+                                                    Only in LP_SLEEP mode, select RTC_SLOW_CLK as the clock source;
+                                                    In other non-LP_SLEEP mode, select RTC_FAST_CLK as the clock source; */
     SOC_MOD_CLK_LP_PERI,                       /*!< LP_PERI_CLK is derived from LP_DYN_FAST (configurable divider) */
     SOC_MOD_CLK_INVALID,                       /*!< Indication of the end of the available module clock sources */
 } soc_module_clk_t;

components/soc/esp32p4/include/soc/periph_defs.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -69,9 +69,14 @@ typedef enum {
     PERIPH_UHCI_MODULE,
     PERIPH_PCNT_MODULE,
     PERIPH_ASSIST_DEBUG_MODULE,
+
     /* LP peripherals */
     PERIPH_LP_I2C0_MODULE,
     PERIPH_LP_UART0_MODULE,
+
+    /* MISC */
+    PERIPH_ANA_I2C_MASTER_MODULE,
+
     PERIPH_MODULE_MAX
 } periph_module_t;
 

components/soc/esp32p4/include/soc/soc_caps.h

@@ -728,7 +728,6 @@
 
 /*-------------------------- CLOCK SUBSYSTEM CAPS ----------------------------------------*/
 #define SOC_CLK_RC_FAST_SUPPORT_CALIBRATION       (1)
-#define SOC_MODEM_CLOCK_IS_INDEPENDENT            (0)
 
 #define SOC_CLK_APLL_SUPPORTED                    (1)     /*!< Support Audio PLL */
 #define SOC_CLK_MPLL_SUPPORTED                    (1)     /*!< Support MSPI PLL */
@@ -738,9 +737,10 @@
 #define SOC_CLK_LP_FAST_SUPPORT_LP_PLL            (1)      /*!< Support LP_PLL clock as the LP_FAST clock source */
 #define SOC_CLK_LP_FAST_SUPPORT_XTAL              (1)     /*!< Support XTAL clock as the LP_FAST clock source */
 
-
 #define SOC_PERIPH_CLK_CTRL_SHARED                (1)     /*!< Peripheral clock control (e.g. set clock source) is shared between various peripherals */
 
+#define SOC_CLK_ANA_I2C_MST_HAS_ROOT_GATE         (1)     /*!< Any regi2c operation needs enable the analog i2c master clock first */
+
 /*-------------------------- Temperature Sensor CAPS -------------------------------------*/
 #define SOC_TEMPERATURE_SENSOR_LP_PLL_SUPPORT                (1)
 #define SOC_TEMPERATURE_SENSOR_INTR_SUPPORT                  (1)