feat(clk): add basic clock support for esp32p4

- Support CPU frequency 360MHz
- Support SOC ROOT clock source switch
- Support LP SLOW clock source switch
- Support clock calibration

components/bootloader_support/src/esp32p4/bootloader_esp32p4.c

@@ -44,6 +44,8 @@
 #include "hal/lpwdt_ll.h"
 #include "soc/lp_wdt_reg.h"
 #include "hal/efuse_hal.h"
+#include "soc/regi2c_syspll.h"
+#include "soc/regi2c_cpll.h"
 
 static const char *TAG = "boot.esp32p4";
 
@@ -88,10 +90,15 @@ static void bootloader_super_wdt_auto_feed(void)
 
 static inline void bootloader_hardware_init(void)
 {
-    //TODO: IDF-7528
-    // /* Enable analog i2c master clock */
-    // SET_PERI_REG_MASK(MODEM_LPCON_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_EN);
-    // SET_PERI_REG_MASK(MODEM_LPCON_I2C_MST_CLK_CONF_REG, MODEM_LPCON_CLK_I2C_MST_SEL_160M);
+    // regi2c is enabled by default on ESP32P4, do nothing
+
+    // On ESP32P4 ECO0, the default (power on reset) CPLL and SPLL frequencies are very high, lower them to avoid bias may not be enough in bootloader
+    // And we are fixing SPLL to be 480MHz at all runtime
+    // Suppose to fix the issue on ECO1, will check when chip comes back
+    // TODO: IDF-8939
+    REGI2C_WRITE_MASK(I2C_CPLL, I2C_CPLL_OC_DIV_7_0, 6); // lower default cpu_pll freq to 400M
+    REGI2C_WRITE_MASK(I2C_SYSPLL, I2C_SYSPLL_OC_DIV_7_0, 8); // lower default sys_pll freq to 480M
+    esp_rom_delay_us(100);
 }
 
 static inline void bootloader_ana_reset_config(void)