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spi_master:support octal mode for esp32s2 and esp32s3

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Add support for 8-line spi for lcd on esp32s2 and esp32s3

Closes https://github.com/espressif/esp-idf/issues/6371
This commit is contained in:
bizhuangyang
2021-07-09 16:46:27 +08:00
committed by morris
parent c81d45280e
commit 8143832041
30 changed files with 709 additions and 414 deletions
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83
components/hal/esp32/include/hal/spi_ll.h
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@@ -28,6 +28,7 @@
#include "esp32/rom/lldesc.h"
#include "soc/spi_periph.h"
#include "hal/misc.h"
#include "hal/spi_types.h"
#ifdef __cplusplus
extern "C" {
@@ -37,6 +38,9 @@ extern "C" {
#define SPI_LL_DMA_FIFO_RST_MASK (SPI_AHBM_RST | SPI_AHBM_FIFO_RST)
/// Interrupt not used. Don't use in app.
#define SPI_LL_UNUSED_INT_MASK (SPI_INT_EN | SPI_SLV_WR_STA_DONE | SPI_SLV_RD_STA_DONE | SPI_SLV_WR_BUF_DONE | SPI_SLV_RD_BUF_DONE)
/// These 2 masks together will set SPI transaction to one line mode
#define SPI_LL_ONE_LINE_CTRL_MASK (SPI_FREAD_DUAL | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_QIO)
#define SPI_LL_ONE_LINE_USER_MASK (SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO)
/// Swap the bit order to its correct place to send
#define HAL_SPI_SWAP_DATA_TX(data, len) HAL_SWAP32((uint32_t)(data) << (32 - len))
/// This is the expected clock frequency
@@ -53,16 +57,6 @@ typedef uint32_t spi_ll_clock_val_t;
//On ESP32-S2 and earlier chips, DMA registers are part of SPI registers. So set the registers of SPI peripheral to control DMA.
typedef spi_dev_t spi_dma_dev_t;
/** IO modes supported by the master. */
typedef enum {
SPI_LL_IO_MODE_NORMAL = 0, ///< 1-bit mode for all phases
SPI_LL_IO_MODE_DIO, ///< 2-bit mode for address and data phases, 1-bit mode for command phase
SPI_LL_IO_MODE_DUAL, ///< 2-bit mode for data phases only, 1-bit mode for command and address phases
SPI_LL_IO_MODE_QIO, ///< 4-bit mode for address and data phases, 1-bit mode for command phase
SPI_LL_IO_MODE_QUAD, ///< 4-bit mode for data phases only, 1-bit mode for command and address phases
} spi_ll_io_mode_t;
/*------------------------------------------------------------------------------
* Control
*----------------------------------------------------------------------------*/
@@ -449,37 +443,50 @@ static inline void spi_ll_set_sio_mode(spi_dev_t *hw, int sio_mode)
}
/**
* Configure the io mode for the master to work at.
* Configure the SPI transaction line mode for the master to use.
*
* @param hw Beginning address of the peripheral registers.
* @param io_mode IO mode to work at, see ``spi_ll_io_mode_t``.
* @param hw Beginning address of the peripheral registers.
* @param line_mode SPI transaction line mode to use, see ``spi_line_mode_t``.
*/
static inline void spi_ll_master_set_io_mode(spi_dev_t *hw, spi_ll_io_mode_t io_mode)
static inline void spi_ll_master_set_line_mode(spi_dev_t *hw, spi_line_mode_t line_mode)
{
hw->ctrl.val &= ~(SPI_FREAD_DUAL | SPI_FREAD_QUAD | SPI_FREAD_DIO | SPI_FREAD_QIO);
hw->user.val &= ~(SPI_FWRITE_DUAL | SPI_FWRITE_QUAD | SPI_FWRITE_DIO | SPI_FWRITE_QIO);
switch (io_mode) {
case SPI_LL_IO_MODE_DIO:
hw->ctrl.fread_dio = 1;
hw->user.fwrite_dio = 1;
break;
case SPI_LL_IO_MODE_DUAL:
hw->ctrl.fread_dual = 1;
hw->user.fwrite_dual = 1;
break;
case SPI_LL_IO_MODE_QIO:
hw->ctrl.fread_qio = 1;
hw->user.fwrite_qio = 1;
break;
case SPI_LL_IO_MODE_QUAD:
hw->ctrl.fread_quad = 1;
hw->user.fwrite_quad = 1;
break;
default:
break;
};
if (io_mode != SPI_LL_IO_MODE_NORMAL) {
hw->ctrl.fastrd_mode = 1;
hw->ctrl.val &= ~SPI_LL_ONE_LINE_CTRL_MASK;
hw->user.val &= ~SPI_LL_ONE_LINE_USER_MASK;
if (line_mode.cmd_lines > 1) {
abort();
}
switch (line_mode.data_lines) {
case 2:
if (line_mode.addr_lines == 1) {
// 1-line-cmd + 1-line-addr + 2-line-data
hw->ctrl.fread_dual = 1;
hw->user.fwrite_dual = 1;
} else if (line_mode.addr_lines == 2) {
// 1-line-cmd + 2-line-addr + 2-line-data
hw->ctrl.fread_dio = 1;
hw->user.fwrite_dio = 1;
} else {
abort();
}
hw->ctrl.fastrd_mode = 1;
break;
case 4:
if (line_mode.addr_lines == 1) {
// 1-line-cmd + 1-line-addr + 4-line-data
hw->ctrl.fread_quad = 1;
hw->user.fwrite_quad = 1;
} else if (line_mode.addr_lines == 4) {
// 1-line-cmd + 4-line-addr + 4-line-data
hw->ctrl.fread_qio = 1;
hw->user.fwrite_qio = 1;
} else {
abort();
}
hw->ctrl.fastrd_mode = 1;
break;
default:
// 1-line-cmd + 1-line-addr + 1-line-data
break;
}
}