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fix(esp_hw_support): iomux slp_sel is not avaliable to isolate mspi pin leakage on esp32p4

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This commit is contained in:
wuzhenghui
2025-03-20 17:59:35 +08:00
parent 61064b442a
commit 821631bd35
3 changed files with 8 additions and 3 deletions
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6
components/esp_hw_support/sleep_gpio.c
View File

@@ -63,7 +63,7 @@ void esp_sleep_config_gpio_isolate(void)
} }
} }
#if CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU #if CONFIG_ESP_SLEEP_MSPI_NEED_ALL_IO_PU && !SOC_MSPI_HAS_INDEPENT_IOMUX
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CLK), GPIO_PULLUP_ONLY); gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_CLK), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_Q), GPIO_PULLUP_ONLY); gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_Q), GPIO_PULLUP_ONLY);
gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D), GPIO_PULLUP_ONLY); gpio_sleep_set_pull_mode(esp_mspi_get_io(ESP_MSPI_IO_D), GPIO_PULLUP_ONLY);
@@ -103,14 +103,14 @@ void esp_sleep_enable_gpio_switch(bool enable)
} }
#endif #endif
/* If the PSRAM is disable in ESP32xx chips equipped with PSRAM, there will be a large current leakage. */ /* If the PSRAM is disable in ESP32xx chips equipped with PSRAM, there will be a large current leakage. */
#if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM #if CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM & !SOC_MSPI_HAS_INDEPENT_IOMUX
if (gpio_num == esp_mspi_get_io(ESP_MSPI_IO_CS1)) { if (gpio_num == esp_mspi_get_io(ESP_MSPI_IO_CS1)) {
gpio_sleep_sel_dis(gpio_num); gpio_sleep_sel_dis(gpio_num);
continue; continue;
} }
#endif // CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM #endif // CONFIG_ESP_SLEEP_PSRAM_LEAKAGE_WORKAROUND && CONFIG_SPIRAM
#if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND #if CONFIG_ESP_SLEEP_FLASH_LEAKAGE_WORKAROUND & !SOC_MSPI_HAS_INDEPENT_IOMUX
if (gpio_num == esp_mspi_get_io(ESP_MSPI_IO_CS0)) { if (gpio_num == esp_mspi_get_io(ESP_MSPI_IO_CS0)) {
gpio_sleep_sel_dis(gpio_num); gpio_sleep_sel_dis(gpio_num);
continue; continue;

4
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1551,6 +1551,10 @@ config SOC_SPI_SUPPORT_CLK_SPLL
bool bool
default y default y
config SOC_MSPI_HAS_INDEPENT_IOMUX
bool
default y
config SOC_MEMSPI_IS_INDEPENDENT config SOC_MEMSPI_IS_INDEPENDENT
bool bool
default y default y

1
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -573,6 +573,7 @@
// host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2, // host_id = 0 -> SPI0/SPI1, host_id = 1 -> SPI2,
#define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;}) #define SOC_SPI_PERIPH_SUPPORT_MULTILINE_MODE(host_id) ({(void)host_id; 1;})
#define SOC_MSPI_HAS_INDEPENT_IOMUX 1
#define SOC_MEMSPI_IS_INDEPENDENT 1 #define SOC_MEMSPI_IS_INDEPENDENT 1
#define SOC_SPI_MAX_PRE_DIVIDER 16 #define SOC_SPI_MAX_PRE_DIVIDER 16