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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/usb_new_phy_driver_collective_backport_v5.1' into 'release/v5.1'
refactor(usb/host): PHY driver preqrequisite refacotring collective backport (v5.1) See merge request espressif/esp-idf!29791
This commit is contained in:
morris
@@ -1,34 +0,0 @@
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/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "soc/usb_serial_jtag_struct.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Configures the internal PHY for USB_Serial_JTAG
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*
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* @param hw Start address of the USB Serial_JTAG registers
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*/
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static inline void usb_fsls_phy_ll_int_jtag_enable(usb_serial_jtag_dev_t *hw)
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{
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// USB_Serial_JTAG use internal PHY
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hw->conf0.phy_sel = 0;
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// Disable software control USB D+ D- pullup pulldown (Device FS: dp_pullup = 1)
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hw->conf0.pad_pull_override = 0;
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// Enable USB D+ pullup
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hw->conf0.dp_pullup = 1;
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// Enable USB pad function
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hw->conf0.usb_pad_enable = 1;
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}
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#ifdef __cplusplus
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}
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#endif
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@@ -4,23 +4,18 @@
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer of the USB-serial-jtag controller
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#pragma once
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#include <stdbool.h>
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#include "esp_attr.h"
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#include "soc/pcr_struct.h"
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#include "soc/usb_serial_jtag_reg.h"
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#include "soc/usb_serial_jtag_struct.h"
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#include "hal/usb_serial_jtag_types.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------- Macros & Types ----------------------------- */
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//The in and out endpoints are this long.
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#define USB_SERIAL_JTAG_PACKET_SZ_BYTES 64
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#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) //All interrupt mask
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#define USB_SERIAL_JTAG_LL_INTR_MASK (0x7ffff) // All interrupts mask
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// Define USB_SERIAL_JTAG interrupts
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// Note the hardware has more interrupts, but they're only useful for debugging
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@@ -34,6 +29,13 @@ typedef enum {
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USB_SERIAL_JTAG_INTR_EP1_ZERO_PAYLOAD = (1 << 10),
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} usb_serial_jtag_ll_intr_t;
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#ifdef __cplusplus
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extern "C" {
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#endif
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/* ----------------------------- USJ Peripheral ----------------------------- */
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/**
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* @brief Enable the USB_SERIAL_JTAG interrupt based on the given mask.
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*
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@@ -123,7 +125,7 @@ static inline int usb_serial_jtag_ll_read_rxfifo(uint8_t *buf, uint32_t rd_len)
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* is room in the buffer.
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*
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* @param buf The data buffer.
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* @param wr_len The data length needs to be writen.
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* @param wr_len The data length needs to be written.
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*
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* @return Amount of bytes actually written. May be less than wr_len.
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*/
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@@ -177,35 +179,130 @@ static inline void usb_serial_jtag_ll_txfifo_flush(void)
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USB_SERIAL_JTAG.ep1_conf.wr_done=1;
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}
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/**
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* @brief Enable USJ JTAG bridge
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*
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* If enabled, USJ is disconnected from internal JTAG interface. JTAG interface
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* is routed through GPIO matrix instead.
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*
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* @param enable Enable USJ JTAG bridge
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_jtag_bridge(bool enable)
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{
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USB_SERIAL_JTAG.conf0.usb_jtag_bridge_en = enable;
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}
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/* ---------------------------- USB PHY Control ---------------------------- */
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/**
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* @brief Disable usb serial jtag pad during light sleep to avoid current leakage
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* @brief Sets PHY defaults
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*
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* @return Initial configuration of usb serial jtag pad enable before light sleep
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* Some PHY register fields/features of the USJ are redundant on the ESP32-C6.
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* This function those fields are set to the appropriate default values.
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*
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* @param hw Start address of the USB Wrap registers
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*/
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FORCE_INLINE_ATTR bool usb_serial_jtag_ll_pad_backup_and_disable(void)
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_defaults(void)
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{
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bool pad_enabled = USB_SERIAL_JTAG.conf0.usb_pad_enable;
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// Disable USB pad function
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USB_SERIAL_JTAG.conf0.usb_pad_enable = 0;
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return pad_enabled;
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// External FSLS PHY is not supported
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USB_SERIAL_JTAG.conf0.phy_sel = 0;
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USB_SERIAL_JTAG.conf0.usb_pad_enable = 1;
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}
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/**
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* @brief Enable the internal USJ PHY control to D+/D- pad
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* @brief Enables/disables exchanging of the D+/D- pins USB PHY
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*
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* @param enable_pad Enable the USJ PHY control to D+/D- pad
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* @param enable Enables pin exchange, disabled otherwise
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_pad(bool enable_pad)
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pin_exchg(bool enable)
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{
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USB_SERIAL_JTAG.conf0.usb_pad_enable = enable_pad;
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if (enable) {
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USB_SERIAL_JTAG.conf0.exchg_pins = 1;
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USB_SERIAL_JTAG.conf0.exchg_pins_override = 1;
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} else {
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USB_SERIAL_JTAG.conf0.exchg_pins_override = 0;
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USB_SERIAL_JTAG.conf0.exchg_pins = 0;
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}
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}
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/**
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* @brief Enable the bus clock for USB Serial_JTAG module
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* @param clk_en True if enable the clock of USB Serial_JTAG module
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* @brief Enables and sets voltage threshold overrides for USB FSLS PHY single-ended inputs
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*
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* @param vrefh_step High voltage threshold. 0 to 3 indicating 80mV steps from 1.76V to 2V.
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* @param vrefl_step Low voltage threshold. 0 to 3 indicating 80mV steps from 0.8V to 1.04V.
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_vref_override(unsigned int vrefh_step, unsigned int vrefl_step)
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{
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USB_SERIAL_JTAG.conf0.vrefh = vrefh_step;
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USB_SERIAL_JTAG.conf0.vrefl = vrefl_step;
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USB_SERIAL_JTAG.conf0.vref_override = 1;
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}
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/**
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* @brief Disables voltage threshold overrides for USB FSLS PHY single-ended inputs
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_vref_override(void)
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{
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USB_SERIAL_JTAG.conf0.vref_override = 0;
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}
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/**
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* @brief Enable override of USB FSLS PHY's pull up/down resistors
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*
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* @param vals Override values to set
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pull_override(const usb_serial_jtag_pull_override_vals_t *vals)
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{
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USB_SERIAL_JTAG.conf0.dp_pullup = vals->dp_pu;
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USB_SERIAL_JTAG.conf0.dp_pulldown = vals->dp_pd;
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USB_SERIAL_JTAG.conf0.dm_pullup = vals->dm_pu;
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USB_SERIAL_JTAG.conf0.dm_pulldown = vals->dm_pd;
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USB_SERIAL_JTAG.conf0.pad_pull_override = 1;
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}
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/**
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* @brief Disable override of USB FSLS PHY pull up/down resistors
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_disable_pull_override(void)
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{
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USB_SERIAL_JTAG.conf0.pad_pull_override = 0;
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}
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/**
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* @brief Sets the strength of the pullup resistor
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*
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* @param strong True is a ~1.4K pullup, false is a ~2.4K pullup
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_set_pullup_strength(bool strong)
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{
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USB_SERIAL_JTAG.conf0.pullup_value = strong;
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}
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/**
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* @brief Check if USB FSLS PHY pads are enabled
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*
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* @return True if enabled, false otherwise
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*/
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FORCE_INLINE_ATTR bool usb_serial_jtag_ll_phy_is_pad_enabled(void)
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{
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return USB_SERIAL_JTAG.conf0.usb_pad_enable;
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}
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/**
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* @brief Enable the USB FSLS PHY pads
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*
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* @param enable Whether to enable the USB FSLS PHY pads
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_phy_enable_pad(bool enable)
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{
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USB_SERIAL_JTAG.conf0.usb_pad_enable = enable;
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}
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/* ----------------------------- RCC Functions ----------------------------- */
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/**
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* @brief Enable the bus clock for USJ module
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* @param clk_en True if enable the clock of USJ module
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
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{
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@@ -213,7 +310,7 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_enable_bus_clock(bool clk_en)
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}
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/**
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* @brief Reset the usb serial jtag module
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* @brief Reset the USJ module
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*/
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FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
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{
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@@ -222,9 +319,9 @@ FORCE_INLINE_ATTR void usb_serial_jtag_ll_reset_register(void)
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}
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/**
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* Get the enable status USB Serial_JTAG module
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* Get the enable status of the USJ module
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*
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* @return Return true if USB Serial_JTAG module is enabled
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* @return Return true if USJ module is enabled
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*/
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FORCE_INLINE_ATTR bool usb_serial_jtag_ll_module_is_enabled(void)
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{
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