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Merge branch 'feat/support_length_eof' into 'master'

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feat(uhci): Add UHCI support on esp32c5, esp32h2.

See merge request espressif/esp-idf!38794
This commit is contained in:
C.S.M
2025-04-29 14:34:58 +08:00
parent 06520a3c99 bb03892461
commit 8344af1f09
21 changed files with 315 additions and 21 deletions
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49
components/hal/esp32h2/include/hal/uhci_ll.h
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@@ -8,6 +8,7 @@
#include <stdio.h>
#include "hal/uhci_types.h"
#include "soc/uhci_struct.h"
#include "soc/pcr_struct.h"
#include "hal/misc.h"
#ifdef __cplusplus
@@ -15,6 +16,7 @@ extern "C" {
#endif
#define UHCI_LL_GET_HW(num) (((num) == 0) ? (&UHCI0) : (NULL))
#define UHCI_LL_MAX_RECEIVE_PACKET_THRESHOLD (8192)
typedef enum {
UHCI_RX_BREAK_CHR_EOF = 0x1,
@@ -23,10 +25,33 @@ typedef enum {
UHCI_RX_EOF_MAX = 0x7,
} uhci_rxeof_cfg_t;
/**
* @brief Enable the bus clock for UHCI module
*
* @param group_id Group ID
* @param enable true to enable, false to disable
*/
static inline void uhci_ll_enable_bus_clock(int group_id, bool enable)
{
(void)group_id;
PCR.uhci_conf.uhci_clk_en = enable;
}
/**
* @brief Reset the UHCI module
*
* @param group_id Group ID
*/
static inline void uhci_ll_reset_register(int group_id)
{
(void)group_id;
PCR.uhci_conf.uhci_rst_en = 1;
PCR.uhci_conf.uhci_rst_en = 0;
}
static inline void uhci_ll_init(uhci_dev_t *hw)
{
typeof(hw->conf0) conf0_reg;
hw->conf0.clk_en = 1;
conf0_reg.val = 0;
conf0_reg.clk_en = 1;
hw->conf0.val = conf0_reg.val;
@@ -35,8 +60,8 @@ static inline void uhci_ll_init(uhci_dev_t *hw)
static inline void uhci_ll_attach_uart_port(uhci_dev_t *hw, int uart_num)
{
hw->conf0.uart0_ce = (uart_num == 0)? 1: 0;
hw->conf0.uart1_ce = (uart_num == 1)? 1: 0;
hw->conf0.uart0_ce = (uart_num == 0) ? 1 : 0;
hw->conf0.uart1_ce = (uart_num == 1) ? 1 : 0;
}
static inline void uhci_ll_set_seper_chr(uhci_dev_t *hw, uhci_seper_chr_t *seper_char)
@@ -69,12 +94,12 @@ static inline void uhci_ll_set_swflow_ctrl_sub_chr(uhci_dev_t *hw, uhci_swflow_c
typeof(hw->esc_conf3) esc_conf3_reg;
esc_conf3_reg.val = hw->esc_conf3.val;
esc_conf2_reg.esc_seq1 = sub_ctr->xon_chr;
esc_conf2_reg.esc_seq1_char0 = sub_ctr->xon_sub1;
esc_conf2_reg.esc_seq1_char1 = sub_ctr->xon_sub2;
esc_conf3_reg.esc_seq2 = sub_ctr->xoff_chr;
esc_conf3_reg.esc_seq2_char0 = sub_ctr->xoff_sub1;
esc_conf3_reg.esc_seq2_char1 = sub_ctr->xoff_sub2;
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1, sub_ctr->xon_chr);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1_char0, sub_ctr->xon_sub1);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf2_reg, esc_seq1_char1, sub_ctr->xon_sub2);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2, sub_ctr->xoff_chr);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2_char0, sub_ctr->xoff_sub1);
HAL_FORCE_MODIFY_U32_REG_FIELD(esc_conf3_reg, esc_seq2_char1, sub_ctr->xoff_sub2);
escape_conf_reg.tx_11_esc_en = 1;
escape_conf_reg.tx_13_esc_en = 1;
escape_conf_reg.rx_11_esc_en = 1;
@@ -110,7 +135,6 @@ static inline uint32_t uhci_ll_get_intr(uhci_dev_t *hw)
return hw->int_st.val;
}
static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
{
if (eof_mode & UHCI_RX_BREAK_CHR_EOF) {
@@ -124,6 +148,11 @@ static inline void uhci_ll_rx_set_eof_mode(uhci_dev_t *hw, uint32_t eof_mode)
}
}
static inline void uhci_ll_rx_set_packet_threshold(uhci_dev_t *hw, uint16_t length)
{
hw->pkt_thres.pkt_thrs = length;
}
#ifdef __cplusplus
}
#endif