feat(sdm): enhance the thread safety

This commit is contained in:
morris
2025-08-07 10:55:52 +08:00
parent e58562e030
commit 83512e3e7c
63 changed files with 504 additions and 579 deletions

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@@ -623,18 +623,6 @@ config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_HD_BOTH_INOUT_SUPPORTED
bool
default y

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@@ -178,14 +178,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group source clock is APB */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
/**

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@@ -297,11 +297,6 @@
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode
#define SOC_SPI_AS_CS_SUPPORTED 1 //Support to toggle the CS while the clock toggles

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@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance