alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-08-23 17:24:44 +00:00
Code Issues Packages Projects Releases Wiki Activity

feat(sdm): enhance the thread safety

Browse Source
This commit is contained in:
morris
2025-08-07 10:55:52 +08:00
parent e58562e030
commit 83512e3e7c
63 changed files with 504 additions and 579 deletions
Download Patch File Download Diff File Expand all files Collapse all files

11
components/esp_driver_sdm/CMakeLists.txt
View File

@@ -1,17 +1,16 @@
idf_build_get_property(target IDF_TARGET)
if(${target} STREQUAL "linux")
return() # This component is not supported by the POSIX/Linux simulator
endif()
set(srcs)
set(public_include "include")
set(priv_requires esp_pm esp_driver_gpio)
if(CONFIG_SOC_SDM_SUPPORTED)
list(APPEND srcs "src/sdm.c")
endif()
if(${target} STREQUAL "linux")
set(priv_requires "")
else()
set(priv_requires esp_pm esp_driver_gpio)
endif()
idf_component_register(SRCS ${srcs}
INCLUDE_DIRS ${public_include}
PRIV_REQUIRES "${priv_requires}"

23
components/esp_driver_sdm/Kconfig
View File

@@ -1,17 +1,30 @@
menu "ESP-Driver:Sigma Delta Modulator Configurations"
depends on SOC_SDM_SUPPORTED
config SDM_CTRL_FUNC_IN_IRAM
bool "Place SDM control functions into IRAM"
default n
select SDM_OBJ_CACHE_SAFE
help
Place SDM control functions (like set_duty) into IRAM,
Place SDM control functions (like set_pulse_density) into IRAM,
so that these functions can be IRAM-safe and able to be called in the other IRAM interrupt context.
Enabling this option can improve driver performance as well.
config SDM_ENABLE_DEBUG_LOG
bool "Enable debug log"
config SDM_OBJ_CACHE_SAFE
bool
default n
help
whether to enable the debug log message for SDM driver.
Note that, this option only controls the SDM driver log, won't affect other drivers.
This will ensure the SDM object will not be allocated from a memory region
where its cache can be disabled.
config SDM_ENABLE_DEBUG_LOG
bool "Force enable debug log"
default n
help
If enabled, SDM driver will:
1. ignore the global logging settings
2. compile all log messages into the binary
3. set the runtime log level to VERBOSE
Please enable this option by caution, as it will increase the binary size.
endmenu # Sigma Delta Modulator Configurations

5
components/esp_driver_sdm/include/driver/sdm.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,6 +8,7 @@
#include <stdint.h>
#include "hal/sdm_types.h"
#include "hal/gpio_types.h"
#include "esp_err.h"
#ifdef __cplusplus
@@ -23,7 +24,7 @@ typedef struct sdm_channel_t *sdm_channel_handle_t;
* @brief Sigma Delta channel configuration
*/
typedef struct {
int gpio_num; /*!< GPIO number */
gpio_num_t gpio_num; /*!< GPIO number */
sdm_clock_source_t clk_src; /*!< Clock source */
uint32_t sample_rate_hz; /*!< Over sample rate in Hz, it determines the frequency of the carrier pulses */
struct {

211
components/esp_driver_sdm/src/sdm.c
View File

@@ -5,12 +5,13 @@
*/
#include <stdlib.h>
#include <stdatomic.h>
#include <sys/lock.h>
#include "sdkconfig.h"
#if CONFIG_SDM_ENABLE_DEBUG_LOG
// The local log level must be defined before including esp_log.h
// Set the maximum log level for this source file
#define LOG_LOCAL_LEVEL ESP_LOG_DEBUG
#define LOG_LOCAL_LEVEL ESP_LOG_VERBOSE
#endif
#include "freertos/FreeRTOS.h"
#include "esp_attr.h"
@@ -22,23 +23,24 @@
#include "esp_clk_tree.h"
#include "driver/gpio.h"
#include "driver/sdm.h"
#include "soc/sdm_periph.h"
#include "hal/sdm_hal.h"
#include "hal/sdm_ll.h"
#include "hal/hal_utils.h"
#include "soc/sdm_periph.h"
#include "esp_private/esp_clk.h"
#include "esp_private/io_mux.h"
#include "esp_private/gpio.h"
#include "esp_private/sleep_retention.h"
#include "esp_private/esp_gpio_reserve.h"
#if CONFIG_SDM_CTRL_FUNC_IN_IRAM
#if CONFIG_SDM_OBJ_CACHE_SAFE
#define SDM_MEM_ALLOC_CAPS (MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT)
#else
#define SDM_MEM_ALLOC_CAPS MALLOC_CAP_DEFAULT
#endif
#define SDM_PM_LOCK_NAME_LEN_MAX 16
static const char *TAG = "sdm";
///!< Logging settings
#define TAG "sdm"
typedef struct sdm_platform_t sdm_platform_t;
typedef struct sdm_group_t sdm_group_t;
@@ -46,40 +48,40 @@ typedef struct sdm_channel_t sdm_channel_t;
struct sdm_platform_t {
_lock_t mutex; // platform level mutex lock
sdm_group_t *groups[SOC_SDM_GROUPS]; // sdm group pool
int group_ref_counts[SOC_SDM_GROUPS]; // reference count used to protect group install/uninstall
sdm_group_t *groups[SOC_SDM_ATTR(INST_NUM)]; // sdm group pool
int group_ref_counts[SOC_SDM_ATTR(INST_NUM)];// reference count used to protect group install/uninstall
};
struct sdm_group_t {
int group_id; // Group ID, index from 0
portMUX_TYPE spinlock; // to protect per-group register level concurrent access
sdm_hal_context_t hal; // hal context
sdm_channel_t *channels[SOC_SDM_CHANNELS_PER_GROUP]; // array of sdm channels
sdm_channel_t *channels[SOC_SDM_ATTR(CHANS_PER_INST)]; // array of sdm channels
sdm_clock_source_t clk_src; // Clock source
#if CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock; // PM lock, to prevent the system going into light sleep when SDM is running
#endif
};
typedef enum {
SDM_FSM_INIT,
SDM_FSM_ENABLE,
SDM_FSM_WAIT,
} sdm_fsm_t;
struct sdm_channel_t {
sdm_group_t *group; // which group the sdm channel belongs to
uint32_t chan_id; // allocated channel numerical ID
int gpio_num; // GPIO number
gpio_num_t gpio_num; // GPIO number
uint32_t sample_rate_hz; // Sample rate, in Hz
portMUX_TYPE spinlock; // to protect per-channels resources concurrently accessed by task and ISR handler
sdm_fsm_t fsm; // FSM state
#if CONFIG_PM_ENABLE
esp_pm_lock_handle_t pm_lock; // PM lock, for glitch filter, as that module can only be functional under APB
char pm_lock_name[SDM_PM_LOCK_NAME_LEN_MAX]; // pm lock name
#endif
portMUX_TYPE spinlock; // to protect per-channels resources concurrently accessed by tasks
_Atomic sdm_fsm_t fsm; // state machine, to control the API is called in the correct order
};
// sdm driver platform, it's always a singleton
static sdm_platform_t s_platform;
static sdm_group_t *sdm_acquire_group_handle(int group_id)
static sdm_group_t *sdm_acquire_group_handle(int group_id, sdm_clock_source_t clk_src)
{
bool new_group = false;
sdm_group_t *group = NULL;
@@ -94,12 +96,12 @@ static sdm_group_t *sdm_acquire_group_handle(int group_id)
// initialize sdm group members
group->group_id = group_id;
group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
group->clk_src = 0;
group->clk_src = clk_src;
// initialize HAL context
sdm_hal_init(&group->hal, group_id);
// enable clock
// note that, this will enables all the channels' output, and channel can't be disable/enable separately
sdm_ll_enable_clock(group->hal.dev, true);
sdm_hal_init_config_t hal_config = {
.group_id = group_id,
};
sdm_hal_init(&group->hal, &hal_config);
}
} else {
group = s_platform.groups[group_id];
@@ -112,6 +114,17 @@ static sdm_group_t *sdm_acquire_group_handle(int group_id)
if (new_group) {
ESP_LOGD(TAG, "new group (%d) at %p", group_id, group);
#if CONFIG_PM_ENABLE
esp_pm_lock_type_t pm_type = ESP_PM_NO_LIGHT_SLEEP;
#if TIMER_LL_FUNC_CLOCK_SUPPORT_APB
if (clk_src == SDM_CLK_SRC_APB) {
pm_type = ESP_PM_APB_FREQ_MAX;
}
#endif // TIMER_LL_FUNC_CLOCK_SUPPORT_APB
if (esp_pm_lock_create(pm_type, 0, soc_sdm_signals[group_id].module_name, &group->pm_lock) != ESP_OK) {
ESP_LOGE(TAG, "fail to create PM lock for group %d", group_id);
}
#endif // CONFIG_PM_ENABLE
}
return group;
@@ -128,29 +141,36 @@ static void sdm_release_group_handle(sdm_group_t *group)
assert(s_platform.groups[group_id]);
do_deinitialize = true;
s_platform.groups[group_id] = NULL; // deregister from platform
sdm_ll_enable_clock(group->hal.dev, false);
sdm_hal_deinit(&group->hal);
}
_lock_release(&s_platform.mutex);
if (do_deinitialize) {
#if CONFIG_PM_ENABLE
if (group->pm_lock) {
esp_pm_lock_delete(group->pm_lock);
}
#endif
free(group);
ESP_LOGD(TAG, "del group (%d)", group_id);
}
}
static esp_err_t sdm_register_to_group(sdm_channel_t *chan)
static esp_err_t sdm_register_to_group(sdm_channel_t *chan, sdm_clock_source_t clk_src)
{
sdm_group_t *group = NULL;
int chan_id = -1;
for (int i = 0; i < SOC_SDM_GROUPS; i++) {
group = sdm_acquire_group_handle(i);
for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) {
group = sdm_acquire_group_handle(i, clk_src);
ESP_RETURN_ON_FALSE(group, ESP_ERR_NO_MEM, TAG, "no mem for group (%d)", i);
// loop to search free unit in the group
portENTER_CRITICAL(&group->spinlock);
for (int j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++) {
for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) {
if (!group->channels[j]) {
chan_id = j;
group->channels[j] = chan;
chan->group = group;
chan->chan_id = chan_id;
break;
}
}
@@ -158,8 +178,6 @@ static esp_err_t sdm_register_to_group(sdm_channel_t *chan)
if (chan_id < 0) {
sdm_release_group_handle(group);
} else {
chan->group = group;
chan->chan_id = chan_id;
break;
}
}
@@ -180,60 +198,53 @@ static void sdm_unregister_from_group(sdm_channel_t *chan)
static esp_err_t sdm_destroy(sdm_channel_t *chan)
{
#if CONFIG_PM_ENABLE
if (chan->pm_lock) {
ESP_RETURN_ON_ERROR(esp_pm_lock_delete(chan->pm_lock), TAG, "delete pm lock failed");
}
#endif
if (chan->group) {
sdm_unregister_from_group(chan);
}
if (chan->gpio_num >= 0) {
gpio_output_disable(chan->gpio_num);
esp_gpio_revoke(BIT64(chan->gpio_num));
}
free(chan);
return ESP_OK;
}
esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_chan)
{
#if CONFIG_SDM_ENABLE_DEBUG_LOG
esp_log_level_set(TAG, ESP_LOG_DEBUG);
#endif
esp_err_t ret = ESP_OK;
sdm_channel_t *chan = NULL;
ESP_GOTO_ON_FALSE(config && ret_chan, ESP_ERR_INVALID_ARG, err, TAG, "invalid argument");
ESP_GOTO_ON_FALSE(GPIO_IS_VALID_OUTPUT_GPIO(config->gpio_num), ESP_ERR_INVALID_ARG, err, TAG, "invalid GPIO number");
ESP_RETURN_ON_FALSE(config && ret_chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(GPIO_IS_VALID_OUTPUT_GPIO(config->gpio_num), ESP_ERR_INVALID_ARG, TAG, "invalid GPIO number");
chan = heap_caps_calloc(1, sizeof(sdm_channel_t), SDM_MEM_ALLOC_CAPS);
ESP_GOTO_ON_FALSE(chan, ESP_ERR_NO_MEM, err, TAG, "no mem for channel");
// allocate channel memory from internal memory because it contains atomic variable
chan = heap_caps_calloc(1, sizeof(sdm_channel_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
ESP_RETURN_ON_FALSE(chan, ESP_ERR_NO_MEM, TAG, "no mem for channel");
chan->gpio_num = GPIO_NUM_NC; // default to NC, will be set later
sdm_clock_source_t clk_src = config->clk_src ? config->clk_src : SDM_CLK_SRC_DEFAULT;
// register channel to the group
ESP_GOTO_ON_ERROR(sdm_register_to_group(chan), err, TAG, "register to group failed");
ESP_GOTO_ON_ERROR(sdm_register_to_group(chan, clk_src), err, TAG, "register to group failed");
sdm_group_t *group = chan->group;
int group_id = group->group_id;
int chan_id = chan->chan_id;
ESP_GOTO_ON_FALSE(group->clk_src == 0 || group->clk_src == config->clk_src, ESP_ERR_INVALID_ARG, err, TAG, "clock source conflict");
uint32_t src_clk_hz = 0;
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)config->clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), err, TAG, "get source clock frequency failed");
#if CONFIG_PM_ENABLE
esp_pm_lock_type_t pm_type = ESP_PM_NO_LIGHT_SLEEP;
#if SOC_SDM_CLK_SUPPORT_APB
if (config->clk_src == SDM_CLK_SRC_APB) {
pm_type = ESP_PM_APB_FREQ_MAX;
}
#endif // SOC_SDM_CLK_SUPPORT_APB
sprintf(chan->pm_lock_name, "sdm_%d_%d", group->group_id, chan_id); // e.g. sdm_0_0
ret = esp_pm_lock_create(pm_type, 0, chan->pm_lock_name, &chan->pm_lock);
ESP_GOTO_ON_ERROR(ret, err, TAG, "create %s lock failed", chan->pm_lock_name);
#endif // CONFIG_PM_ENABLE
group->clk_src = config->clk_src;
ESP_GOTO_ON_FALSE(group->clk_src == clk_src, ESP_ERR_INVALID_ARG, err, TAG, "clock source conflict");
// SDM clock comes from IO MUX, but IO MUX clock might be shared with other submodules as well
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)(group->clk_src)), err, TAG, "set IO MUX clock source failed");
ESP_GOTO_ON_ERROR(io_mux_set_clock_source((soc_module_clk_t)clk_src), err, TAG, "set IO MUX clock source failed");
gpio_func_sel(config->gpio_num, PIN_FUNC_GPIO);
// connect the signal to the GPIO by matrix, it will also enable the output path properly
esp_rom_gpio_connect_out_signal(config->gpio_num, sigma_delta_periph_signals.channels[chan_id].sd_sig, config->flags.invert_out, false);
uint32_t src_clk_hz = 0;
ESP_GOTO_ON_ERROR(esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src,
ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &src_clk_hz), err, TAG, "get source clock frequency failed");
// Reserve the new GPIO
uint64_t old_gpio_rsv_mask = esp_gpio_reserve(BIT64(config->gpio_num));
if (old_gpio_rsv_mask & BIT64(config->gpio_num)) {
ESP_LOGW(TAG, "GPIO %d is not usable, maybe conflict with others", config->gpio_num);
}
// connect the signal to the GPIO by matrix
gpio_matrix_output(config->gpio_num, soc_sdm_signals[group_id].channels[chan_id].sig_id_matrix, config->flags.invert_out, false);
chan->gpio_num = config->gpio_num;
// set prescale based on sample rate
@@ -258,7 +269,7 @@ esp_err_t sdm_new_channel(const sdm_config_t *config, sdm_channel_handle_t *ret_
// initialize other members of timer
chan->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
chan->fsm = SDM_FSM_INIT; // put the channel into init state
atomic_init(&chan->fsm, SDM_FSM_INIT); // set the initial state to INIT
ESP_LOGD(TAG, "new sdm channel (%d,%d) at %p, gpio=%d, sample rate=%"PRIu32"Hz", group_id, chan_id, chan, chan->gpio_num, chan->sample_rate_hz);
*ret_chan = chan;
@@ -273,12 +284,10 @@ err:
esp_err_t sdm_del_channel(sdm_channel_handle_t chan)
{
ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(chan->fsm == SDM_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state");
sdm_group_t *group = chan->group;
int group_id = group->group_id;
int chan_id = chan->chan_id;
gpio_output_disable(chan->gpio_num);
ESP_LOGD(TAG, "del channel (%d,%d)", group_id, chan_id);
sdm_fsm_t expected_fsm = SDM_FSM_INIT;
ESP_RETURN_ON_FALSE(atomic_compare_exchange_strong(&chan->fsm, &expected_fsm, SDM_FSM_WAIT),
ESP_ERR_INVALID_STATE, TAG, "channel not in init state");
ESP_LOGD(TAG, "del channel (%d,%d)", chan->group->group_id, chan->chan_id);
// recycle memory resource
ESP_RETURN_ON_ERROR(sdm_destroy(chan), TAG, "destroy channel failed");
return ESP_OK;
@@ -287,36 +296,66 @@ esp_err_t sdm_del_channel(sdm_channel_handle_t chan)
esp_err_t sdm_channel_enable(sdm_channel_handle_t chan)
{
ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(chan->fsm == SDM_FSM_INIT, ESP_ERR_INVALID_STATE, TAG, "channel not in init state");
sdm_fsm_t expected_fsm = SDM_FSM_INIT;
if (atomic_compare_exchange_strong(&chan->fsm, &expected_fsm, SDM_FSM_WAIT)) {
#if CONFIG_PM_ENABLE
// acquire power manager lock
if (chan->pm_lock) {
ESP_RETURN_ON_ERROR(esp_pm_lock_acquire(chan->pm_lock), TAG, "acquire pm_lock failed");
if (chan->group->pm_lock) {
esp_pm_lock_acquire(chan->group->pm_lock);
}
#endif
chan->fsm = SDM_FSM_ENABLE;
// enable the channel
atomic_store(&chan->fsm, SDM_FSM_ENABLE); // change state to ENABLE
ESP_LOGD(TAG, "channel (%d,%d) enabled", chan->group->group_id, chan->chan_id);
} else {
ESP_RETURN_ON_ERROR(ESP_ERR_INVALID_STATE, TAG, "channel not in init state");
}
return ESP_OK;
}
esp_err_t sdm_channel_disable(sdm_channel_handle_t chan)
{
ESP_RETURN_ON_FALSE(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
ESP_RETURN_ON_FALSE(chan->fsm == SDM_FSM_ENABLE, ESP_ERR_INVALID_STATE, TAG, "channel not in enable state");
sdm_fsm_t expected_fsm = SDM_FSM_ENABLE;
if (atomic_compare_exchange_strong(&chan->fsm, &expected_fsm, SDM_FSM_WAIT)) {
#if CONFIG_PM_ENABLE
// release power manager lock
if (chan->pm_lock) {
ESP_RETURN_ON_ERROR(esp_pm_lock_release(chan->pm_lock), TAG, "release pm_lock failed");
if (chan->group->pm_lock) {
esp_pm_lock_release(chan->group->pm_lock);
}
#endif
chan->fsm = SDM_FSM_INIT;
atomic_store(&chan->fsm, SDM_FSM_INIT); // change state to INIT
ESP_LOGD(TAG, "channel (%d,%d) disabled", chan->group->group_id, chan->chan_id);
} else {
ESP_RETURN_ON_ERROR(ESP_ERR_INVALID_STATE, TAG, "channel not in enable state");
}
return ESP_OK;
}
esp_err_t sdm_channel_set_pulse_density(sdm_channel_handle_t chan, int8_t density)
{
ESP_RETURN_ON_FALSE_ISR(chan, ESP_ERR_INVALID_ARG, TAG, "invalid argument");
if (!chan) {
return ESP_ERR_INVALID_ARG;
}
bool valid_state = false;
sdm_fsm_t expected_fsm = SDM_FSM_INIT;
sdm_fsm_t restore_fsm = SDM_FSM_INIT;
// check if the channel is in INIT state, if so, change it to WAIT state
if (atomic_compare_exchange_strong(&chan->fsm, &expected_fsm, SDM_FSM_WAIT)) {
valid_state = true;
restore_fsm = SDM_FSM_INIT;
} else {
expected_fsm = SDM_FSM_ENABLE;
if (atomic_compare_exchange_strong(&chan->fsm, &expected_fsm, SDM_FSM_WAIT)) {
valid_state = true;
restore_fsm = SDM_FSM_ENABLE;
}
}
if (!valid_state) {
return ESP_ERR_INVALID_STATE;
}
sdm_group_t *group = chan->group;
int chan_id = chan->chan_id;
@@ -325,8 +364,18 @@ esp_err_t sdm_channel_set_pulse_density(sdm_channel_handle_t chan, int8_t densit
sdm_ll_set_pulse_density(group->hal.dev, chan_id, density);
portEXIT_CRITICAL_SAFE(&chan->spinlock);
atomic_store(&chan->fsm, restore_fsm); // restore the state
return ESP_OK;
}
esp_err_t sdm_channel_set_duty(sdm_channel_handle_t chan, int8_t duty)
__attribute__((alias("sdm_channel_set_pulse_density")));
#if CONFIG_SDM_ENABLE_DEBUG_LOG
__attribute__((constructor))
static void sdm_override_default_log_level(void)
{
esp_log_level_set(TAG, ESP_LOG_VERBOSE);
}
#endif

2
components/esp_driver_sdm/test_apps/sigma_delta/main/CMakeLists.txt
View File

@@ -1,7 +1,7 @@
set(srcs "test_app_main.c")
if(CONFIG_SOC_SDM_SUPPORTED)
list(APPEND srcs "test_sdm.c")
list(APPEND srcs "test_sdm.cpp")
endif()
# In order for the cases defined by `TEST_CASE` to be linked into the final elf,

25
components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.c → components/esp_driver_sdm/test_apps/sigma_delta/main/test_sdm.cpp
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -10,28 +10,31 @@
#include "freertos/task.h"
#include "unity.h"
#include "driver/sdm.h"
#include "soc/soc_caps.h"
#include "soc/sdm_periph.h"
#include "esp_attr.h"
TEST_CASE("sdm_channel_install_uninstall", "[sdm]")
{
printf("install sdm channels exhaustively\r\n");
sdm_config_t config = {
.gpio_num = GPIO_NUM_0,
.clk_src = SDM_CLK_SRC_DEFAULT,
.sample_rate_hz = 1000000,
.gpio_num = 0,
.flags = {
.invert_out = false,
},
};
sdm_channel_handle_t chans[SOC_SDM_GROUPS][SOC_SDM_CHANNELS_PER_GROUP] = {};
for (int i = 0; i < SOC_SDM_GROUPS; i++) {
for (int j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++) {
sdm_channel_handle_t chans[SOC_SDM_ATTR(INST_NUM)][SOC_SDM_ATTR(CHANS_PER_INST)] = {};
for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) {
for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) {
TEST_ESP_OK(sdm_new_channel(&config, &chans[i][j]));
}
TEST_ESP_ERR(ESP_ERR_NOT_FOUND, sdm_new_channel(&config, &chans[0][0]));
}
printf("delete sdm channels\r\n");
for (int i = 0; i < SOC_SDM_GROUPS; i++) {
for (int j = 0; j < SOC_SDM_CHANNELS_PER_GROUP; j++) {
for (int i = 0; i < SOC_SDM_ATTR(INST_NUM); i++) {
for (int j = 0; j < SOC_SDM_ATTR(CHANS_PER_INST); j++) {
TEST_ESP_OK(sdm_del_channel(chans[i][j]));
}
}
@@ -39,10 +42,14 @@ TEST_CASE("sdm_channel_install_uninstall", "[sdm]")
TEST_CASE("sdm_channel_set_pulse_density", "[sdm]")
{
const int sdm_chan_gpios[2] = {0, 2};
const gpio_num_t sdm_chan_gpios[2] = {GPIO_NUM_0, GPIO_NUM_2};
sdm_config_t config = {
.gpio_num = GPIO_NUM_NC, // will be set later
.clk_src = SDM_CLK_SRC_DEFAULT,
.sample_rate_hz = 1000000,
.flags = {
.invert_out = false,
},
};
sdm_channel_handle_t chans[2] = {};
for (size_t i = 0; i < 2; i++) {

3
components/esp_driver_sdm/test_apps/sigma_delta/pytest_sigma_delta.py
View File

@@ -3,6 +3,7 @@
import pytest
from pytest_embedded_idf import IdfDut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
CONFIGS = [
'iram_safe',
@@ -14,7 +15,7 @@ CONFIGS = [
@pytest.mark.parametrize('config', CONFIGS, indirect=True)
@idf_parametrize(
'target',
['esp32', 'esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32s2', 'esp32s3', 'esp32h2', 'esp32p4'],
soc_filtered_targets('SOC_SDM_SUPPORTED == 1'),
indirect=['target'],
)
def test_sdm(dut: IdfDut) -> None:

8
components/hal/esp32/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,8 +16,14 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1)
// Support APB as function clock
#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1
/**
* @brief Set Sigma-delta enable
*

8
components/hal/esp32c3/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,8 +16,14 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1)
// Support APB as function clock
#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1
/**
* @brief Set Sigma-delta enable
*

5
components/hal/esp32c5/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,9 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1)
/**

5
components/hal/esp32c6/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,9 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1)
/**

5
components/hal/esp32h2/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,9 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1)
/**

5
components/hal/esp32p4/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,6 +16,9 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_EXT_SD0_PRESCALE_V + 1)
/**

8
components/hal/esp32s2/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,8 +16,14 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1)
// Support APB as function clock
#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1
/**
* @brief Set Sigma-delta enable
*

8
components/hal/esp32s3/include/hal/sdm_ll.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -16,8 +16,14 @@
extern "C" {
#endif
// Get SDM register base address with giving group number
#define SDM_LL_GET_HW(group_id) ((group_id == 0) ? (&SDM) : NULL)
#define SDM_LL_PRESCALE_MAX (GPIO_SD0_PRESCALE_V + 1)
// Support APB as function clock
#define SDM_LL_FUNC_CLOCK_SUPPORT_APB 1
/**
* @brief Set Sigma-delta enable
*

26
components/hal/include/hal/sdm_hal.h
View File

@@ -1,15 +1,9 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
/*******************************************************************************
* NOTICE
* The hal is not public api, don't use in application code.
* See readme.md in hal/include/hal/readme.md
******************************************************************************/
// The HAL layer for sigma delta modulator.
// There is no parameter check in the hal layer, so the caller must ensure the correctness of the parameters.
@@ -28,13 +22,27 @@ typedef struct {
sdm_soc_handle_t dev;
} sdm_hal_context_t;
/**
* @brief Configuration for the Sigma-Delta HAL layer initialization
*/
typedef struct {
int group_id; // Group ID, index from 0
} sdm_hal_init_config_t;
/**
* @brief Initialize Sigma-Delta hal driver
*
* @param hal Context of the HAL layer
* @param group_id Sigma-Delta group number
* @param config Configuration for the HAL layer initialization
*/
void sdm_hal_init(sdm_hal_context_t *hal, int group_id);
void sdm_hal_init(sdm_hal_context_t *hal, const sdm_hal_init_config_t *config);
/**
* @brief Deinitialize Sigma-Delta hal driver
*
* @param hal Context of the HAL layer
*/
void sdm_hal_deinit(sdm_hal_context_t *hal);
#ifdef __cplusplus
}

21
components/hal/sdm_hal.c
View File

@@ -1,16 +1,25 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
// The HAL layer for sigma delta modulator (common part)
#include "hal/sdm_ll.h"
#include "hal/sdm_hal.h"
void sdm_hal_init(sdm_hal_context_t *hal, int group_id)
void sdm_hal_init(sdm_hal_context_t *hal, const sdm_hal_init_config_t *config)
{
(void) group_id;
hal->dev = &SDM;
hal->dev = SDM_LL_GET_HW(config->group_id);
// enable clock
// note that, this will enables all the channels' output, and channel can't be disable/enable separately
sdm_ll_enable_clock(hal->dev, true);
}
void sdm_hal_deinit(sdm_hal_context_t *hal)
{
if (hal && hal->dev) {
// disable clock
sdm_ll_enable_clock(hal->dev, false);
hal->dev = NULL;
}
}

12
components/soc/esp32/include/soc/Kconfig.soc_caps.in
View File

@@ -623,18 +623,6 @@ config SOC_RTCIO_WAKE_SUPPORTED
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_HD_BOTH_INOUT_SUPPORTED
bool
default y

8
components/soc/esp32/include/soc/clk_tree_defs.h
View File

@@ -178,14 +178,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group source clock is APB */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
/**

5
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -297,11 +297,6 @@
#define SOC_RTCIO_HOLD_SUPPORTED 1
#define SOC_RTCIO_WAKE_SUPPORTED 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode
#define SOC_SPI_AS_CS_SUPPORTED 1 //Support to toggle the CS while the clock toggles

4
components/soc/esp32/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance

23
components/soc/esp32/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,31 +7,34 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
},
[4] = {
GPIO_SD4_OUT_IDX
.sig_id_matrix = GPIO_SD4_OUT_IDX
},
[5] = {
GPIO_SD5_OUT_IDX
.sig_id_matrix = GPIO_SD5_OUT_IDX
},
[6] = {
GPIO_SD6_OUT_IDX
.sig_id_matrix = GPIO_SD6_OUT_IDX
},
[7] = {
GPIO_SD7_OUT_IDX
.sig_id_matrix = GPIO_SD7_OUT_IDX
}
}
}
};

9
components/soc/esp32c2/include/soc/clk_tree_defs.h
View File

@@ -175,15 +175,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< Select PLL_F40M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F40M = SOC_MOD_CLK_PLL_F40M, /*!< Timer group clock source is PLL_F40M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F40M, /*!< Timer group clock source default choice is PLL_F40M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**

12
components/soc/esp32c3/include/soc/Kconfig.soc_caps.in
View File

@@ -707,18 +707,6 @@ config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

9
components/soc/esp32c3/include/soc/clk_tree_defs.h
View File

@@ -171,15 +171,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group clock source is APB */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group clock source default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**

7
components/soc/esp32c3/include/soc/soc_caps.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -309,11 +309,6 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6

4
components/soc/esp32c3/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance

15
components/soc/esp32c3/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,19 +7,22 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
}
}
}
};

16
components/soc/esp32c5/include/soc/Kconfig.soc_caps.in
View File

@@ -1127,22 +1127,6 @@ config SOC_ECDSA_SUPPORT_CURVE_P384
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

9
components/soc/esp32c5/include/soc/clk_tree_defs.h
View File

@@ -192,15 +192,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**

6
components/soc/esp32c5/include/soc/soc_caps.h
View File

@@ -444,12 +444,6 @@
#define SOC_ECDSA_SUPPORT_HW_DETERMINISTIC_LOOP (1)
#define SOC_ECDSA_SUPPORT_CURVE_P384 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6

4
components/soc/esp32c5/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance

15
components/soc/esp32c5/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,19 +7,22 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
}
}
}
};

16
components/soc/esp32c6/include/soc/Kconfig.soc_caps.in
View File

@@ -987,22 +987,6 @@ config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

9
components/soc/esp32c6/include/soc/clk_tree_defs.h
View File

@@ -189,15 +189,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**

6
components/soc/esp32c6/include/soc/soc_caps.h
View File

@@ -394,12 +394,6 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6

4
components/soc/esp32c6/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance

15
components/soc/esp32c6/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,19 +7,22 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
}
}
}
};

9
components/soc/esp32c61/include/soc/clk_tree_defs.h
View File

@@ -180,15 +180,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Select PLL_F80M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////Temp Sensor///////////////////////////////////////////////////////////
/**

16
components/soc/esp32h2/include/soc/Kconfig.soc_caps.in
View File

@@ -1003,22 +1003,6 @@ config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F48M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

9
components/soc/esp32h2/include/soc/clk_tree_defs.h
View File

@@ -198,15 +198,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source default choice is PLL_F48M */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**

6
components/soc/esp32h2/include/soc/soc_caps.h
View File

@@ -412,12 +412,6 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F48M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6

4
components/soc/esp32h2/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 4 // Number of channels in each SDM instance

15
components/soc/esp32h2/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,19 +7,22 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
}
}
}
};

13
components/soc/esp32h21/include/soc/clk_tree_defs.h
View File

@@ -187,19 +187,6 @@ typedef enum {
#endif
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F48M = SOC_MOD_CLK_PLL_F48M, /*!< Timer group clock source is PLL_F48M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
#if SOC_CLK_TREE_SUPPORTED
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F48M, /*!< Select PLL_F48M as the default choice */
#else
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Select XTAL as the default choice if no clk_tree */
#endif
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**

16
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
View File

@@ -1499,22 +1499,6 @@ config SOC_ECDSA_USES_MPI
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3

13
components/soc/esp32p4/include/soc/clk_tree_defs.h
View File

@@ -230,19 +230,6 @@ typedef enum {
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_PLL_F80M = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source is PLL_F80M */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group clock source is XTAL */
#if SOC_CLK_TREE_SUPPORTED
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_PLL_F80M, /*!< Timer group clock source default choice is PLL_F80M */
#else
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_XTAL, /*!< Timer group clock source default choice is XTAL */
#endif // SOC_CLK_TREE_SUPPORTED
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////RMT///////////////////////////////////////////////////////////////////
/**

6
components/soc/esp32p4/include/soc/soc_caps.h
View File

@@ -555,12 +555,6 @@
#define SOC_ECDSA_SUPPORT_DETERMINISTIC_MODE (1)
#define SOC_ECDSA_USES_MPI (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))

4
components/soc/esp32p4/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance

23
components/soc/esp32p4/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,31 +7,34 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
},
[4] = {
GPIO_SD4_OUT_IDX
.sig_id_matrix = GPIO_SD4_OUT_IDX
},
[5] = {
GPIO_SD5_OUT_IDX
.sig_id_matrix = GPIO_SD5_OUT_IDX
},
[6] = {
GPIO_SD6_OUT_IDX
.sig_id_matrix = GPIO_SD6_OUT_IDX
},
[7] = {
GPIO_SD7_OUT_IDX
.sig_id_matrix = GPIO_SD7_OUT_IDX
}
}
}
};

12
components/soc/esp32s2/include/soc/Kconfig.soc_caps.in
View File

@@ -671,18 +671,6 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_HD_BOTH_INOUT_SUPPORTED
bool
default y

9
components/soc/esp32s2/include/soc/clk_tree_defs.h
View File

@@ -174,15 +174,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group source clock is APB */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group source clock is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
/**

5
components/soc/esp32s2/include/soc/soc_caps.h
View File

@@ -289,11 +289,6 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_HD_BOTH_INOUT_SUPPORTED 1 //Support enabling MOSI and MISO phases together under Halfduplex mode
#define SOC_SPI_PERIPH_NUM 3

4
components/soc/esp32s2/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance

23
components/soc/esp32s2/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,31 +7,34 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
},
[4] = {
GPIO_SD4_OUT_IDX
.sig_id_matrix = GPIO_SD4_OUT_IDX
},
[5] = {
GPIO_SD5_OUT_IDX
.sig_id_matrix = GPIO_SD5_OUT_IDX
},
[6] = {
GPIO_SD6_OUT_IDX
.sig_id_matrix = GPIO_SD6_OUT_IDX
},
[7] = {
GPIO_SD7_OUT_IDX
.sig_id_matrix = GPIO_SD7_OUT_IDX
}
}
}
};

12
components/soc/esp32s3/include/soc/Kconfig.soc_caps.in
View File

@@ -859,18 +859,6 @@ config SOC_LP_IO_CLOCK_IS_INDEPENDENT
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 8
config SOC_SDM_CLK_SUPPORT_APB
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 3

9
components/soc/esp32s3/include/soc/clk_tree_defs.h
View File

@@ -173,15 +173,6 @@ typedef enum {
GPTIMER_CLK_SRC_DEFAULT = SOC_MOD_CLK_APB, /*!< Select APB as the default choice */
} soc_periph_gptimer_clk_src_t;
/**
* @brief Type of Timer Group clock source, reserved for the legacy timer group driver
*/
typedef enum {
TIMER_SRC_CLK_APB = SOC_MOD_CLK_APB, /*!< Timer group source clock is APB */
TIMER_SRC_CLK_XTAL = SOC_MOD_CLK_XTAL, /*!< Timer group source clock is XTAL */
TIMER_SRC_CLK_DEFAULT = SOC_MOD_CLK_APB, /*!< Timer group source clock default choice is APB */
} soc_periph_tg_clk_src_legacy_t;
//////////////////////////////////////////////////LCD///////////////////////////////////////////////////////////////////
/**

5
components/soc/esp32s3/include/soc/soc_caps.h
View File

@@ -341,11 +341,6 @@
// LP IO peripherals have independent clock gating to manage
#define SOC_LP_IO_CLOCK_IS_INDEPENDENT 1
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS (1U)
#define SOC_SDM_CHANNELS_PER_GROUP 8
#define SOC_SDM_CLK_SUPPORT_APB 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 3
#define SOC_SPI_PERIPH_CS_NUM(i) (((i)==0)? 2: (((i)==1)? 6: 3))

4
components/soc/esp32s3/include/soc/soc_caps_full.h
View File

@@ -19,3 +19,7 @@
/*--------------------------- Watch Dog ------------------------------------------*/
#define _SOC_CAPS_WDT_MWDTS_PER_TIMG 1 // Number of main watchdog timers in each Timer Group
/*--------------------------- SDM (Sigma-Delta Modulator) ------------------------*/
#define _SOC_CAPS_SDM_INST_NUM 1 // Number of SDM instances
#define _SOC_CAPS_SDM_CHANS_PER_INST 8 // Number of channels in each SDM instance

23
components/soc/esp32s3/sdm_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -7,31 +7,34 @@
#include "soc/sdm_periph.h"
#include "soc/gpio_sig_map.h"
const sigma_delta_signal_conn_t sigma_delta_periph_signals = {
const soc_sdm_signal_desc_t soc_sdm_signals[1] = {
[0] = {
.module_name = "SDM0",
.channels = {
[0] = {
GPIO_SD0_OUT_IDX
.sig_id_matrix = GPIO_SD0_OUT_IDX
},
[1] = {
GPIO_SD1_OUT_IDX
.sig_id_matrix = GPIO_SD1_OUT_IDX
},
[2] = {
GPIO_SD2_OUT_IDX
.sig_id_matrix = GPIO_SD2_OUT_IDX
},
[3] = {
GPIO_SD3_OUT_IDX
.sig_id_matrix = GPIO_SD3_OUT_IDX
},
[4] = {
GPIO_SD4_OUT_IDX
.sig_id_matrix = GPIO_SD4_OUT_IDX
},
[5] = {
GPIO_SD5_OUT_IDX
.sig_id_matrix = GPIO_SD5_OUT_IDX
},
[6] = {
GPIO_SD6_OUT_IDX
.sig_id_matrix = GPIO_SD6_OUT_IDX
},
[7] = {
GPIO_SD7_OUT_IDX
.sig_id_matrix = GPIO_SD7_OUT_IDX
}
}
}
};

28
components/soc/include/soc/sdm_periph.h
View File

@@ -1,28 +1,36 @@
/*
* SPDX-FileCopyrightText: 2019-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/soc_caps.h"
#include <stdint.h>
#include <stddef.h>
#include "soc/soc_caps_full.h"
#include "soc/periph_defs.h"
#include "soc/regdma.h"
#if SOC_HAS(PAU)
#include "soc/retention_periph_defs.h"
#endif // SOC_HAS(PAU)
// helper macros to access module attributes
#define SOC_SDM_ATTR(_attr) SOC_MODULE_ATTR(SDM, _attr)
#ifdef __cplusplus
extern "C" {
#endif
#if SOC_SDM_SUPPORTED
typedef struct {
const char *module_name; // Module name
struct {
const int sd_sig;
} channels[SOC_SDM_CHANNELS_PER_GROUP];
} sigma_delta_signal_conn_t;
const int sig_id_matrix; // signal ID in the GPIO matrix
} channels[SOC_SDM_ATTR(CHANS_PER_INST)];
} soc_sdm_signal_desc_t;
extern const sigma_delta_signal_conn_t sigma_delta_periph_signals;
#endif // SOC_SDM_SUPPORTED
extern const soc_sdm_signal_desc_t soc_sdm_signals[SOC_SDM_ATTR(INST_NUM)];
#ifdef __cplusplus
}

8
docs/en/api-reference/peripherals/sdm.rst
View File

@@ -102,13 +102,13 @@ There is a Kconfig option :ref:`CONFIG_SDM_CTRL_FUNC_IN_IRAM` that can put commo
Thread Safety
^^^^^^^^^^^^^
The factory function :cpp:func:`sdm_new_channel` is guaranteed to be thread-safe by the driver, which means, the user can call it from different RTOS tasks without protection by extra locks.
The driver uses critical sections to ensure atomic operations on registers. Key members in the driver handle are also protected by critical sections. The driver's internal state machine uses atomic instructions to ensure thread safety, with state checks preventing certain invalid concurrent operations (e.g., conflicts between `enable` and `delete`). Therefore, SDM driver APIs can be used in a multi-threaded environment without extra locking.
The following functions are allowed to run under ISR context, the driver uses a critical section to prevent them being called concurrently in both task and ISR.
The following functions can also be used in an interrupt context:
- :cpp:func:`sdm_channel_set_pulse_density`
.. list::
Other functions that take the :cpp:type:`sdm_channel_handle_t` as the first positional parameter, are not treated as thread-safe. This means the user should avoid calling them from multiple tasks.
- :cpp:func:`sdm_channel_set_pulse_density`
.. _sdm-kconfig-options:

8
docs/zh_CN/api-reference/peripherals/sdm.rst
View File

@@ -102,13 +102,13 @@ Kconfig 选项 :ref:`CONFIG_SDM_CTRL_FUNC_IN_IRAM` 支持将常用的 IO 控制
线程安全
^^^^^^^^
驱动程序会确保工厂函数 :cpp:func:`sdm_new_channel` 的线程安全，使用时，可以直接从不同的 RTOS 任务中调用此类函数，无需额外锁保护。
驱动使用了临界区保证了对寄存器的原子操作。句柄内部的关键成员也受临界区保护。驱动内部的状态机使用了原子指令保证了线程安全，通过状态检查还能进一步防止一些不合法的并发操作（例如 `enable` 和 `delete` 冲突）。因此， SDM 驱动的 API 可以在多线程环境下使用，无需自行加锁。
驱动程序设置了临界区，以防函数同时在任务和 ISR 中调用。因此，以下函数支持在 ISR 上下文运行：
同时，以下这些函数还允许在中断上下文中使用：
- :cpp:func:`sdm_channel_set_pulse_density`
.. list::
其他以 :cpp:type:`sdm_channel_handle_t` 作为第一个位置参数的函数均非线程安全，因此应避免从多个任务中调用这类函数。
- :cpp:func:`sdm_channel_set_pulse_density`
.. _sdm-kconfig-options: