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Merge branch 'feature/uart_dtr_dsr_support' into 'master'

Browse Source 
feat(uart): add DTR and DSR signals support for UART

Closes IDF-13392, IDFGH-4377, and IDFGH-15328

See merge request espressif/esp-idf!40508
This commit is contained in:
Song Ruo Jing
2025-08-07 17:28:28 +08:00
parent 2319386d9d c6dad68e81
commit 8651d6c240
42 changed files with 1030 additions and 349 deletions
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18
components/soc/esp32c5/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,24 +8,27 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 12
#define U0TXD_GPIO_NUM 11
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 4
#define LP_U0TXD_GPIO_NUM 5
#define LP_U0RTS_GPIO_NUM 2
#define LP_U0CTS_GPIO_NUM 3
#define LP_U0DTR_GPIO_NUM 0
#define LP_U0DSR_GPIO_NUM 1
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -34,13 +37,20 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (0)
#define LP_U0RXD_MUX_FUNC (0)
#define LP_U0RTS_MUX_FUNC (0)
#define LP_U0CTS_MUX_FUNC (0)
#define LP_U0DTR_MUX_FUNC (0)
#define LP_U0DSR_MUX_FUNC (0)

70
components/soc/esp32c5/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,33 +13,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
@@ -47,33 +61,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
@@ -81,33 +109,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// LP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = LP_U0DTR_GPIO_NUM,
.iomux_func = LP_U0DTR_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = LP_U0DSR_GPIO_NUM,
.iomux_func = LP_U0DSR_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
},