alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-09-02 22:51:14 +00:00
Code Issues Packages Projects Releases Wiki Activity

Merge branch 'feature/uart_dtr_dsr_support' into 'master'

Browse Source 
feat(uart): add DTR and DSR signals support for UART

Closes IDF-13392, IDFGH-4377, and IDFGH-15328

See merge request espressif/esp-idf!40508
This commit is contained in:
Song Ruo Jing
2025-08-07 17:28:28 +08:00
parent 2319386d9d c6dad68e81
commit 8651d6c240
42 changed files with 1030 additions and 349 deletions
Download Patch File Download Diff File Expand all files Collapse all files

33
components/soc/esp32s3/include/soc/uart_pins.h
View File

@@ -1,39 +1,34 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define U0CTS_GPIO_NUM 16
#define U0RTS_GPIO_NUM 15
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U1CTS_GPIO_NUM 20
#define U1RTS_GPIO_NUM 19
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define U2RXD_GPIO_NUM (-1)
#define U2TXD_GPIO_NUM (-1)
#define U2CTS_GPIO_NUM (-1)
#define U2RTS_GPIO_NUM (-1)
#define U2DTR_GPIO_NUM (-1)
#define U2DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -41,11 +36,15 @@
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
#define U0RTS_MUX_FUNC (FUNC_XTAL_32K_P_U0RTS)
#define U0CTS_MUX_FUNC (FUNC_XTAL_32K_N_U0CTS)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
#define U1TXD_MUX_FUNC (FUNC_DAC_1_U1TXD)
#define U1RXD_MUX_FUNC (FUNC_DAC_2_U1RXD)
#define U1RTS_MUX_FUNC (FUNC_GPIO19_U1RTS)
#define U1CTS_MUX_FUNC (FUNC_GPIO20_U1CTS)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
/* UART2 cannot be used directly through the IOMUX, these value
* shall not be used. */
@@ -53,3 +52,5 @@
#define U2RXD_MUX_FUNC (-1)
#define U2RTS_MUX_FUNC (-1)
#define U2CTS_MUX_FUNC (-1)
#define U2DTR_MUX_FUNC (-1)
#define U2DSR_MUX_FUNC (-1)

72
components/soc/esp32s3/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,99 +12,141 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = U2TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = U2RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = U2RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = U2CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U2DTR_GPIO_NUM,
.iomux_func = U2DTR_MUX_FUNC,
.input = 0,
.signal = U2DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U2DSR_GPIO_NUM,
.iomux_func = U2DSR_MUX_FUNC,
.input = 1,
.signal = U2DSR_IN_IDX,
},
},
.irq = ETS_UART2_INTR_SOURCE,
}