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Merge branch 'feature/uart_dtr_dsr_support' into 'master'

Browse Source 
feat(uart): add DTR and DSR signals support for UART

Closes IDF-13392, IDFGH-4377, and IDFGH-15328

See merge request espressif/esp-idf!40508
This commit is contained in:
Song Ruo Jing
2025-08-07 17:28:28 +08:00
parent 2319386d9d c6dad68e81
commit 8651d6c240
42 changed files with 1030 additions and 349 deletions
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6
components/bootloader_support/src/bootloader_console.c
View File

@@ -30,7 +30,7 @@ static void __attribute__((unused)) release_default_console_io(void)
{
// Default console is UART0 with TX and RX on their IOMUX pins
gpio_ll_output_disable(&GPIO, U0TXD_GPIO_NUM);
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(UART_NUM_0, SOC_UART_RX_PIN_IDX), 0);
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(UART_NUM_0, SOC_UART_PERIPH_SIGNAL_RX), 0);
}
#ifdef CONFIG_ESP_CONSOLE_NONE
@@ -72,8 +72,8 @@ void bootloader_console_init(void)
uart_rx_gpio != U0RXD_GPIO_NUM) {
release_default_console_io();
// Route GPIO signals to/from pins
const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX);
const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX);
const uint32_t tx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX);
const uint32_t rx_idx = UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX);
gpio_ll_func_sel(&GPIO, uart_rx_gpio, PIN_FUNC_GPIO);
gpio_ll_input_enable(&GPIO, uart_rx_gpio);
esp_rom_gpio_pad_pullup_only(uart_rx_gpio);

2
components/driver/test_apps/legacy_i2c_driver/main/test_i2c.c
View File

@@ -679,7 +679,7 @@ static void uart_aut_baud_det_init(int rxd_io_num)
gpio_func_sel(rxd_io_num, PIN_FUNC_GPIO);
gpio_set_direction(rxd_io_num, GPIO_MODE_INPUT_OUTPUT);
esp_rom_gpio_connect_out_signal(rxd_io_num, i2c_periph_signal[0].scl_out_sig, 0, 0);
esp_rom_gpio_connect_in_signal(rxd_io_num, UART_PERIPH_SIGNAL(1, SOC_UART_RX_PIN_IDX), 0);
esp_rom_gpio_connect_in_signal(rxd_io_num, UART_PERIPH_SIGNAL(1, SOC_UART_PERIPH_SIGNAL_RX), 0);
HP_UART_BUS_CLK_ATOMIC() {
uart_ll_enable_bus_clock(1, true);
uart_ll_reset_register(1);

40
components/esp_driver_uart/include/driver/uart.h
View File

@@ -7,11 +7,11 @@
#pragma once
#include "esp_err.h"
#include "esp_intr_alloc.h"
#include "soc/soc_caps.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "hal/uart_types.h"
#include "esp_check.h"
#ifdef __cplusplus
extern "C" {
@@ -22,7 +22,6 @@ extern "C" {
*/
#define UART_PIN_NO_CHANGE (-1)
#define UART_FIFO_LEN _Pragma ("GCC warning \"'UART_FIFO_LEN' macro is deprecated, please use 'UART_HW_FIFO_LEN' instead\"") SOC_UART_FIFO_LEN ///< Length of the HP UART HW FIFO
#if (SOC_UART_LP_NUM >= 1)
#define UART_HW_FIFO_LEN(uart_num) ((uart_num < SOC_UART_HP_NUM) ? SOC_UART_FIFO_LEN : SOC_LP_UART_FIFO_LEN) ///< Length of the UART HW FIFO
#else
@@ -94,8 +93,6 @@ typedef struct {
/*!< If the event is caused by FIFO-full interrupt, then there will be no event with the timeout flag before the next byte coming.*/
} uart_event_t;
typedef intr_handle_t uart_isr_handle_t;
/**
* @brief Install UART driver and set the UART to the default configuration.
*
@@ -390,6 +387,23 @@ esp_err_t uart_disable_tx_intr(uart_port_t uart_num);
*/
esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh);
// Function declarations for different argument counts
esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num, int dtr_io_num, int dsr_io_num);
static inline esp_err_t _uart_set_pin4(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num)
{
return _uart_set_pin6(uart_num, tx_io_num, rx_io_num, rts_io_num, cts_io_num, -1, -1);
}
// Error function for invalid argument count
static inline esp_err_t __uart_set_pin_invalid_args__(int dummy, ...)
{
ESP_RETURN_ON_FALSE(false, ESP_FAIL, "uart", "Invalid number of arguments to uart_set_pin(). Expected 5 or 7 arguments.");
return ESP_OK;
}
// Argument counting macro
#define _GET_UART_SET_PIN_FUNC_NAME(_1, _2, _3, _4, _5, _6, _7, _FUNC_NAME, ...) _FUNC_NAME
/**
* @brief Assign signals of a UART peripheral to GPIO pins
*
@@ -410,17 +424,23 @@ esp_err_t uart_enable_tx_intr(uart_port_t uart_num, int enable, int thresh);
* Apply open-drain and pull-up to the pad ahead of time as a protection,
* or the upper layer protocol must guarantee no output from two ends at the same time.
*
* @param uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* @param tx_io_num UART TX pin GPIO number.
* @param rx_io_num UART RX pin GPIO number.
* @param rts_io_num UART RTS pin GPIO number.
* @param cts_io_num UART CTS pin GPIO number.
* @note Variadic arguments
* - param: uart_num UART port number, the max port number is (UART_NUM_MAX -1).
* - param: tx_io_num UART TX pin GPIO number.
* - param: rx_io_num UART RX pin GPIO number.
* - param: rts_io_num UART RTS pin GPIO number.
* - param: cts_io_num UART CTS pin GPIO number.
* - param: dtr_io_num UART DTR pin GPIO number (optional). DTR signal is automatically controlled by hardware when UART is in RS485 mode.
* - param: dsr_io_num UART DSR pin GPIO number (optional).
*
* @return
* - ESP_OK Success
* - ESP_FAIL Parameter error
*/
esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num);
#define uart_set_pin(...) \
_GET_UART_SET_PIN_FUNC_NAME(__VA_ARGS__, \
_uart_set_pin6, __uart_set_pin_invalid_args__, _uart_set_pin4, \
__uart_set_pin_invalid_args__, __uart_set_pin_invalid_args__, __uart_set_pin_invalid_args__)(__VA_ARGS__)
/**
* @brief Manually set the UART RTS pin level.

125
components/esp_driver_uart/src/uart.c
View File

@@ -11,7 +11,6 @@
#include "esp_intr_alloc.h"
#include "esp_log.h"
#include "esp_err.h"
#include "esp_check.h"
#include "freertos/FreeRTOS.h"
#include "freertos/queue.h"
#include "freertos/semphr.h"
@@ -116,6 +115,8 @@ static const char *UART_TAG = "uart";
.rx_io_num = -1, \
.rts_io_num = -1, \
.cts_io_num = -1, \
.dtr_io_num = -1, \
.dsr_io_num = -1, \
.io_reserved_mask = 0, \
}
@@ -183,6 +184,8 @@ typedef struct uart_context_t {
int rx_io_num;
int rts_io_num;
int cts_io_num;
int dtr_io_num;
int dsr_io_num;
uint64_t io_reserved_mask;
} uart_context_t;
@@ -722,7 +725,7 @@ static bool uart_try_set_iomux_pin(uart_port_t uart_num, int io_num, uint32_t id
return true;
}
static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release_rx, bool release_rts, bool release_cts)
static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release_rx, bool release_rts, bool release_cts, bool release_dtr, bool release_dsr)
{
if (uart_num >= UART_NUM_MAX) {
return;
@@ -746,12 +749,12 @@ static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release
if (release_rx && uart_context[uart_num].rx_io_num >= 0) {
if (uart_num < SOC_UART_HP_NUM) {
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false);
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
}
#if (SOC_UART_LP_NUM >= 1)
else {
#if SOC_LP_GPIO_MATRIX_SUPPORTED
lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false);
lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ONE_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
#endif
rtc_gpio_deinit(uart_context[uart_num].rx_io_num);
}
@@ -778,12 +781,12 @@ static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release
if (release_cts && uart_context[uart_num].cts_io_num >= 0) {
if (uart_num < SOC_UART_HP_NUM) {
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false);
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_CTS), false);
}
#if (SOC_UART_LP_NUM >= 1)
else {
#if SOC_LP_GPIO_MATRIX_SUPPORTED
lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false);
lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_CTS), false);
#endif
rtc_gpio_deinit(uart_context[uart_num].cts_io_num);
}
@@ -793,11 +796,40 @@ static void uart_release_pin(uart_port_t uart_num, bool release_tx, bool release
uart_context[uart_num].cts_io_num = -1;
}
if (release_dtr && uart_context[uart_num].dtr_io_num >= 0) {
gpio_output_disable(uart_context[uart_num].dtr_io_num);
#if (SOC_UART_LP_NUM >= 1)
if (!(uart_num < SOC_UART_HP_NUM)) {
rtc_gpio_deinit(uart_context[uart_num].dtr_io_num);
}
#endif
released_io_mask |= BIT64(uart_context[uart_num].dtr_io_num);
uart_context[uart_num].dtr_io_num = -1;
}
if (release_dsr && uart_context[uart_num].dsr_io_num >= 0) {
if (uart_num < SOC_UART_HP_NUM) {
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DSR), false);
}
#if (SOC_UART_LP_NUM >= 1)
else {
#if SOC_LP_GPIO_MATRIX_SUPPORTED
lp_gpio_connect_in_signal(LP_GPIO_MATRIX_CONST_ZERO_INPUT, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DSR), false);
#endif
rtc_gpio_deinit(uart_context[uart_num].dsr_io_num);
}
#endif
released_io_mask |= BIT64(uart_context[uart_num].dsr_io_num);
uart_context[uart_num].dsr_io_num = -1;
}
esp_gpio_revoke(uart_context[uart_num].io_reserved_mask & released_io_mask);
uart_context[uart_num].io_reserved_mask &= ~released_io_mask;
}
esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num)
esp_err_t _uart_set_pin6(uart_port_t uart_num, int tx_io_num, int rx_io_num, int rts_io_num, int cts_io_num, int dtr_io_num, int dsr_io_num)
{
ESP_RETURN_ON_FALSE((uart_num >= 0), ESP_FAIL, UART_TAG, "uart_num error");
ESP_RETURN_ON_FALSE((uart_num < UART_NUM_MAX), ESP_FAIL, UART_TAG, "uart_num error");
@@ -806,6 +838,11 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (GPIO_IS_VALID_GPIO(rx_io_num))), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(rts_io_num))), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (GPIO_IS_VALID_GPIO(cts_io_num))), ESP_FAIL, UART_TAG, "cts_io_num error");
#if CONFIG_IDF_TARGET_ESP32
ESP_RETURN_ON_FALSE(!((uart_num > UART_NUM_0) && (dtr_io_num >= 0 || dsr_io_num >= 0)), ESP_FAIL, UART_TAG, "no DTR and DSR signals on the specified UART port");
#endif
ESP_RETURN_ON_FALSE((dtr_io_num < 0 || (GPIO_IS_VALID_OUTPUT_GPIO(dtr_io_num))), ESP_FAIL, UART_TAG, "dtr_io_num error");
ESP_RETURN_ON_FALSE((dsr_io_num < 0 || (GPIO_IS_VALID_GPIO(dsr_io_num))), ESP_FAIL, UART_TAG, "dsr_io_num error");
}
#if (SOC_UART_LP_NUM >= 1)
else { // LP_UART IO check
@@ -813,23 +850,26 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
const uart_periph_sig_t *pins = uart_periph_signal[uart_num].pins;
// LP_UART has its fixed IOs
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (rx_io_num == pins[SOC_UART_RX_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (rts_io_num == pins[SOC_UART_RTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (cts_io_num == pins[SOC_UART_CTS_PIN_IDX].default_gpio)), ESP_FAIL, UART_TAG, "cts_io_num error");
ESP_RETURN_ON_FALSE((tx_io_num < 0 || (tx_io_num == pins[SOC_UART_PERIPH_SIGNAL_TX].default_gpio)), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || (rx_io_num == pins[SOC_UART_PERIPH_SIGNAL_RX].default_gpio)), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || (rts_io_num == pins[SOC_UART_PERIPH_SIGNAL_RTS].default_gpio)), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || (cts_io_num == pins[SOC_UART_PERIPH_SIGNAL_CTS].default_gpio)), ESP_FAIL, UART_TAG, "cts_io_num error");
ESP_RETURN_ON_FALSE((dtr_io_num < 0 || (dtr_io_num == pins[SOC_UART_PERIPH_SIGNAL_DTR].default_gpio)), ESP_FAIL, UART_TAG, "dtr_io_num error");
ESP_RETURN_ON_FALSE((dsr_io_num < 0 || (dsr_io_num == pins[SOC_UART_PERIPH_SIGNAL_DSR].default_gpio)), ESP_FAIL, UART_TAG, "dsr_io_num error");
#else
// LP_UART signals can be routed to any LP_IOs
ESP_RETURN_ON_FALSE((tx_io_num < 0 || rtc_gpio_is_valid_gpio(tx_io_num)), ESP_FAIL, UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((rx_io_num < 0 || rtc_gpio_is_valid_gpio(rx_io_num)), ESP_FAIL, UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((rts_io_num < 0 || rtc_gpio_is_valid_gpio(rts_io_num)), ESP_FAIL, UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cts_io_num < 0 || rtc_gpio_is_valid_gpio(cts_io_num)), ESP_FAIL, UART_TAG, "cts_io_num error");
ESP_RETURN_ON_FALSE((dtr_io_num < 0 || rtc_gpio_is_valid_gpio(dtr_io_num)), ESP_FAIL, UART_TAG, "dtr_io_num error");
ESP_RETURN_ON_FALSE((dsr_io_num < 0 || rtc_gpio_is_valid_gpio(dsr_io_num)), ESP_FAIL, UART_TAG, "dsr_io_num error");
#endif // SOC_LP_GPIO_MATRIX_SUPPORTED
}
#endif
// First, release previously configured IOs if there is
uart_release_pin(uart_num, (tx_io_num >= 0), (rx_io_num >= 0), (rts_io_num >= 0), (cts_io_num >= 0));
uart_release_pin(uart_num, (tx_io_num >= 0), (rx_io_num >= 0), (rts_io_num >= 0), (cts_io_num >= 0), (dtr_io_num >= 0), (dsr_io_num >= 0));
// Potential IO reserved mask
uint64_t io_reserve_mask = 0;
@@ -837,6 +877,8 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
io_reserve_mask |= (rx_io_num > 0 ? BIT64(rx_io_num) : 0);
io_reserve_mask |= (rts_io_num > 0 ? BIT64(rts_io_num) : 0);
io_reserve_mask |= (cts_io_num > 0 ? BIT64(cts_io_num) : 0);
io_reserve_mask |= (dtr_io_num > 0 ? BIT64(dtr_io_num) : 0);
io_reserve_mask |= (dsr_io_num > 0 ? BIT64(dsr_io_num) : 0);
// Since an IO cannot route peripheral signals via IOMUX and GPIO matrix at the same time,
// if tx and rx share the same IO, both signals need to be route to IOs through GPIO matrix
@@ -851,14 +893,14 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
// Therefore, we should disable the switch of the TX pin to sleep configuration
gpio_sleep_sel_dis(tx_io_num);
#endif
if (tx_rx_same_io || !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_TX_PIN_IDX)) {
if (tx_rx_same_io || !uart_try_set_iomux_pin(uart_num, tx_io_num, SOC_UART_PERIPH_SIGNAL_TX)) {
if (uart_num < SOC_UART_HP_NUM) {
gpio_matrix_output(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), false, false);
gpio_matrix_output(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX), false, false);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
rtc_gpio_init(tx_io_num); // set as a LP_GPIO pin
lp_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_TX_PIN_IDX), 0, 0);
lp_gpio_connect_out_signal(tx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_TX), 0, 0);
// output enable is set inside lp_gpio_connect_out_signal func after the signal is connected
}
#endif
@@ -873,10 +915,10 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
// Therefore, we should disable the switch of the RX pin to sleep configuration
gpio_sleep_sel_dis(rx_io_num);
#endif
if (tx_rx_same_io || !uart_try_set_iomux_pin(uart_num, rx_io_num, SOC_UART_RX_PIN_IDX)) {
if (tx_rx_same_io || !uart_try_set_iomux_pin(uart_num, rx_io_num, SOC_UART_PERIPH_SIGNAL_RX)) {
io_reserve_mask &= ~BIT64(rx_io_num); // input IO via GPIO matrix does not need to be reserved
if (uart_num < SOC_UART_HP_NUM) {
gpio_matrix_input(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), false);
gpio_matrix_input(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), false);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
@@ -886,35 +928,62 @@ esp_err_t uart_set_pin(uart_port_t uart_num, int tx_io_num, int rx_io_num, int r
rtc_gpio_init(rx_io_num); // set as a LP_GPIO pin
}
lp_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RX_PIN_IDX), 0);
lp_gpio_connect_in_signal(rx_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RX), 0);
}
#endif
}
}
if (rts_io_num >= 0 && (uart_context[uart_num].rts_io_num = rts_io_num, !uart_try_set_iomux_pin(uart_num, rts_io_num, SOC_UART_RTS_PIN_IDX))) {
if (rts_io_num >= 0 && (uart_context[uart_num].rts_io_num = rts_io_num, !uart_try_set_iomux_pin(uart_num, rts_io_num, SOC_UART_PERIPH_SIGNAL_RTS))) {
if (uart_num < SOC_UART_HP_NUM) {
gpio_matrix_output(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), false, false);
gpio_matrix_output(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RTS), false, false);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
rtc_gpio_init(rts_io_num); // set as a LP_GPIO pin
lp_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_RTS_PIN_IDX), 0, 0);
lp_gpio_connect_out_signal(rts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_RTS), 0, 0);
// output enable is set inside lp_gpio_connect_out_signal func after the signal is connected
}
#endif
}
if (cts_io_num >= 0 && (uart_context[uart_num].cts_io_num = cts_io_num, !uart_try_set_iomux_pin(uart_num, cts_io_num, SOC_UART_CTS_PIN_IDX))) {
if (cts_io_num >= 0 && (uart_context[uart_num].cts_io_num = cts_io_num, !uart_try_set_iomux_pin(uart_num, cts_io_num, SOC_UART_PERIPH_SIGNAL_CTS))) {
io_reserve_mask &= ~BIT64(cts_io_num); // input IO via GPIO matrix does not need to be reserved
if (uart_num < SOC_UART_HP_NUM) {
gpio_matrix_input(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), false);
gpio_matrix_input(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_CTS), false);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
rtc_gpio_set_direction(cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
rtc_gpio_init(cts_io_num); // set as a LP_GPIO pin
lp_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_CTS_PIN_IDX), 0);
lp_gpio_connect_in_signal(cts_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_CTS), 0);
}
#endif
}
if (dtr_io_num >= 0 && (uart_context[uart_num].dtr_io_num = dtr_io_num, !uart_try_set_iomux_pin(uart_num, dtr_io_num, SOC_UART_PERIPH_SIGNAL_DTR))) {
if (uart_num < SOC_UART_HP_NUM) {
gpio_matrix_output(dtr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DTR), false, false);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
rtc_gpio_init(dtr_io_num); // set as a LP_GPIO pin
lp_gpio_connect_out_signal(dtr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DTR), 0, 0);
// output enable is set inside lp_gpio_connect_out_signal func after the signal is connected
}
#endif
}
if (dsr_io_num >= 0 && (uart_context[uart_num].dsr_io_num = dsr_io_num, !uart_try_set_iomux_pin(uart_num, dsr_io_num, SOC_UART_PERIPH_SIGNAL_DSR))) {
io_reserve_mask &= ~BIT64(dsr_io_num); // input IO via GPIO matrix does not need to be reserved
if (uart_num < SOC_UART_HP_NUM) {
gpio_matrix_input(dsr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DSR), false);
}
#if SOC_LP_GPIO_MATRIX_SUPPORTED
else {
rtc_gpio_set_direction(dsr_io_num, RTC_GPIO_MODE_INPUT_ONLY);
rtc_gpio_init(dsr_io_num); // set as a LP_GPIO pin
lp_gpio_connect_in_signal(dsr_io_num, UART_PERIPH_SIGNAL(uart_num, SOC_UART_PERIPH_SIGNAL_DSR), 0);
}
#endif
}
@@ -1908,7 +1977,7 @@ esp_err_t uart_driver_delete(uart_port_t uart_num)
return ESP_OK;
}
uart_release_pin(uart_num, true, true, true, true);
uart_release_pin(uart_num, true, true, true, true, true, true);
esp_intr_free(p_uart_obj[uart_num]->intr_handle);
uart_disable_rx_intr(uart_num);
@@ -2136,7 +2205,7 @@ esp_err_t uart_detect_bitrate_start(uart_port_t uart_num, const uart_bitrate_det
uart_hal_set_sclk(&(uart_context[uart_num].hal), uart_sclk_sel);
uart_hal_set_baudrate(&(uart_context[uart_num].hal), 57600, sclk_freq); // set to any baudrate
}
uart_set_pin(uart_num, UART_PIN_NO_CHANGE, config->rx_io_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
_uart_set_pin6(uart_num, UART_PIN_NO_CHANGE, config->rx_io_num, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE);
} else if (config != NULL) {
ESP_LOGW(UART_TAG, "unable to re-configure for an acquired port, ignoring the new config");
}
@@ -2187,7 +2256,7 @@ esp_err_t uart_detect_bitrate_stop(uart_port_t uart_num, bool deinit, uart_bitra
}
if (deinit) { // release the port
uart_release_pin(uart_num, true, true, true, true);
uart_release_pin(uart_num, true, true, true, true, true, true);
ESP_RETURN_ON_ERROR(esp_clk_tree_enable_src(uart_context[uart_num].sclk_sel, false), UART_TAG, "clock source disable failed");
#if SOC_UART_SUPPORT_RTC_CLK
if (src_clk == (soc_module_clk_t)UART_SCLK_RTC) {

2
components/esp_driver_uart/test_apps/.build-test-rules.yml
View File

@@ -7,7 +7,7 @@ components/esp_driver_uart/test_apps/rs485:
temporary: true
reason: not support yet # TODO: [ESP32H4] IDF-12398
disable_test:
- if: IDF_TARGET != "esp32"
- if: IDF_TARGET not in ["esp32", "esp32h2"]
temporary: true
reason: lack of runners
depends_components:

26
components/esp_driver_uart/test_apps/rs485/main/test_rs485.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2021-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2021-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,22 +12,30 @@
#include "driver/uart.h" // for the uart driver access
#include "esp_log.h"
#include "esp_random.h" // for uint32_t esp_random()
#include "sdkconfig.h"
#define UART_NUM1 (UART_NUM_1)
#define UART_BAUD_RATE (115200 * 10)
#define BUF_SIZE (512)
#if CONFIG_IDF_TARGET_ESP32
#define UART1_RX_PIN (22)
#define UART1_TX_PIN (23)
// RTS for RS485 Half-Duplex Mode manages DE/~RE
#define UART1_RTS_PIN (18)
// For RS485 Half-Duplex Mode manages DE/~RE
#define RS485_DE_PIN (18) // For ESP32, let's use RTS signal to control DE/~RE pin
#elif CONFIG_IDF_TARGET_ESP32H2
#define UART1_RX_PIN (4)
#define UART1_TX_PIN (5)
// For RS485 Half-Duplex Mode manages DE/~RE
#define RS485_DE_PIN (12) // For ESP32H2, let's use DTR signal to control DE/~RE pin
#endif
// Number of packets to be send during test
#define PACKETS_NUMBER (30)
// Wait timeout for uart driver
#define PACKET_READ_TICS (2000 / portTICK_PERIOD_MS)
// This is for workarond to avoid master-slave synchronization issues
// This is for workaround to avoid master-slave synchronization issues
// when slave gets the "Master_started" signal with delay ~2-3 seconds
#define TEST_ALLOW_PROC_FAIL (10)
#define TEST_CHECK_PROC_FAIL(fails, threshold) TEST_ASSERT((fails * 100 / PACKETS_NUMBER) <= threshold)
@@ -166,7 +174,11 @@ static void rs485_init(void)
// Configure UART1 parameters
TEST_ESP_OK(uart_param_config(UART_NUM1, &uart_config));
// Set UART1 pins
TEST_ESP_OK(uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, UART1_RTS_PIN, UART_PIN_NO_CHANGE));
#if CONFIG_IDF_TARGET_ESP32
TEST_ESP_OK(uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, RS485_DE_PIN, UART_PIN_NO_CHANGE));
#elif CONFIG_IDF_TARGET_ESP32H2
TEST_ESP_OK(uart_set_pin(UART_NUM1, UART1_TX_PIN, UART1_RX_PIN, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, RS485_DE_PIN, UART_PIN_NO_CHANGE));
#endif
// Install UART driver (we don't need an event queue here)
TEST_ESP_OK(uart_driver_install(UART_NUM1, BUF_SIZE * 2, 0, 0, NULL, 0));
// Setup rs485 half duplex mode
@@ -285,4 +297,4 @@ static void rs485_master(void)
* correctness of RS485 interface channel communication. It requires
* RS485 bus driver hardware to be connected to boards.
*/
TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[RS485][test_env=UT_T2_RS485]", rs485_master, rs485_slave);
TEST_CASE_MULTIPLE_DEVICES("RS485 half duplex uart multiple devices test.", "[RS485]", rs485_master, rs485_slave);

2
components/esp_driver_uart/test_apps/rs485/pytest_rs485.py
View File

@@ -15,6 +15,6 @@ from pytest_embedded_idf.utils import idf_parametrize
],
indirect=True,
)
@idf_parametrize('target', ['esp32'], indirect=['target'])
@idf_parametrize('target', ['esp32', 'esp32h2'], indirect=['target'])
def test_rs485_multi_dev(case_tester) -> None: # type: ignore
case_tester.run_all_multi_dev_cases(reset=True)

6
components/esp_driver_uart/test_apps/uart/main/test_uart.c
View File

@@ -451,7 +451,7 @@ TEST_CASE("uart int state restored after flush", "[uart]")
.source_clk = port_param.default_src_clk,
};
const int uart_tx_signal = uart_periph_signal[uart_num].pins[SOC_UART_TX_PIN_IDX].signal;
const int uart_tx_signal = uart_periph_signal[uart_num].pins[SOC_UART_PERIPH_SIGNAL_TX].signal;
const int uart_tx = port_param.tx_pin_num;
const int uart_rx = port_param.rx_pin_num;
const int buf_size = 256;
@@ -475,7 +475,7 @@ TEST_CASE("uart int state restored after flush", "[uart]")
// In case the selected RX IO is the LP UART IOMUX IO, and the IO has been configured to IOMUX function in the driver
// Do the following:
TEST_ESP_OK(rtc_gpio_iomux_func_sel(uart_rx, RTCIO_LL_PIN_FUNC));
const int uart_rx_signal = uart_periph_signal[uart_num].pins[SOC_UART_RX_PIN_IDX].signal;
const int uart_rx_signal = uart_periph_signal[uart_num].pins[SOC_UART_PERIPH_SIGNAL_RX].signal;
TEST_ESP_OK(lp_gpio_connect_in_signal(uart_rx, uart_rx_signal, false));
TEST_ESP_OK(lp_gpio_connect_out_signal(uart_rx, uart_tx_signal, false, false));
#else
@@ -610,7 +610,7 @@ TEST_CASE("uart auto baud rate detection", "[uart]")
uint32_t actual_baudrate = 0;
uint32_t detected_baudrate = 0;
uart_bitrate_detect_config_t conf = {
.rx_io_num = uart_periph_signal[CONFIG_CONSOLE_UART_NUM].pins[SOC_UART_TX_PIN_IDX].default_gpio,
.rx_io_num = uart_periph_signal[CONFIG_CONSOLE_UART_NUM].pins[SOC_UART_PERIPH_SIGNAL_TX].default_gpio,
.source_clk = UART_SCLK_DEFAULT,
};
uart_bitrate_res_t res = {};

17
components/soc/esp32/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,24 +8,27 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0TXD_GPIO_NUM (1)
#define U0RXD_GPIO_NUM (3)
#define U0CTS_GPIO_NUM (19)
#define U0RTS_GPIO_NUM (22)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (10)
#define U1RXD_GPIO_NUM (9)
#define U1CTS_GPIO_NUM (6)
#define U1RTS_GPIO_NUM (11)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define U2TXD_GPIO_NUM (17)
#define U2RXD_GPIO_NUM (16)
#define U2CTS_GPIO_NUM (8)
#define U2RTS_GPIO_NUM (7)
#define U2DTR_GPIO_NUM (-1)
#define U2DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -33,13 +36,19 @@
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
#define U0RTS_MUX_FUNC (FUNC_GPIO22_U0RTS)
#define U0CTS_MUX_FUNC (FUNC_GPIO19_U0CTS)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
#define U1TXD_MUX_FUNC (FUNC_SD_DATA3_U1TXD)
#define U1RXD_MUX_FUNC (FUNC_SD_DATA2_U1RXD)
#define U1RTS_MUX_FUNC (FUNC_SD_CMD_U1RTS)
#define U1CTS_MUX_FUNC (FUNC_SD_CLK_U1CTS)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
#define U2TXD_MUX_FUNC (FUNC_GPIO17_U2TXD)
#define U2RXD_MUX_FUNC (FUNC_GPIO16_U2RXD)
#define U2RTS_MUX_FUNC (FUNC_SD_DATA0_U2RTS)
#define U2CTS_MUX_FUNC (FUNC_SD_DATA1_U2CTS)
#define U2DTR_MUX_FUNC (-1)
#define U2DSR_MUX_FUNC (-1)

72
components/soc/esp32/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,99 +12,141 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // No DTR signal on ESP32 UART1
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // No DSR signal on ESP32 UART1
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = U2TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = U2RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = U2RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = U2CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U2DTR_GPIO_NUM,
.iomux_func = U2DTR_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // No DTR signal on ESP32 UART2
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U2DSR_GPIO_NUM,
.iomux_func = U2DSR_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // No DSR signal on ESP32 UART2
},
},
.irq = ETS_UART2_INTR_SOURCE,
}

14
components/soc/esp32c2/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,19 +8,20 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 19
#define U0TXD_GPIO_NUM 20
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -29,8 +30,13 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)

48
components/soc/esp32c2/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,66 +12,94 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},

30
components/soc/esp32c3/include/soc/uart_pins.h
View File

@@ -1,34 +1,27 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 20
#define U0TXD_GPIO_NUM 21
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -37,8 +30,13 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)

48
components/soc/esp32c3/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,66 +12,94 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},

18
components/soc/esp32c5/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,24 +8,27 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 12
#define U0TXD_GPIO_NUM 11
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 4
#define LP_U0TXD_GPIO_NUM 5
#define LP_U0RTS_GPIO_NUM 2
#define LP_U0CTS_GPIO_NUM 3
#define LP_U0DTR_GPIO_NUM 0
#define LP_U0DSR_GPIO_NUM 1
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -34,13 +37,20 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (0)
#define LP_U0RXD_MUX_FUNC (0)
#define LP_U0RTS_MUX_FUNC (0)
#define LP_U0CTS_MUX_FUNC (0)
#define LP_U0DTR_MUX_FUNC (0)
#define LP_U0DSR_MUX_FUNC (0)

70
components/soc/esp32c5/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,33 +13,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
@@ -47,33 +61,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
@@ -81,33 +109,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// LP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = LP_U0DTR_GPIO_NUM,
.iomux_func = LP_U0DTR_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = LP_U0DSR_GPIO_NUM,
.iomux_func = LP_U0DSR_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
},

18
components/soc/esp32c6/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,24 +8,27 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 17
#define U0TXD_GPIO_NUM 16
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 4
#define LP_U0TXD_GPIO_NUM 5
#define LP_U0RTS_GPIO_NUM 2
#define LP_U0CTS_GPIO_NUM 3
#define LP_U0DTR_GPIO_NUM 0
#define LP_U0DSR_GPIO_NUM 1
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -34,13 +37,20 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (1)
#define LP_U0RXD_MUX_FUNC (1)
#define LP_U0RTS_MUX_FUNC (1)
#define LP_U0CTS_MUX_FUNC (1)
#define LP_U0DTR_MUX_FUNC (1)
#define LP_U0DSR_MUX_FUNC (1)

70
components/soc/esp32c6/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,33 +14,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
@@ -48,33 +62,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
@@ -82,33 +110,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// LP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = LP_U0DTR_GPIO_NUM,
.iomux_func = LP_U0DTR_MUX_FUNC,
.input = 0,
.signal = UINT8_MAX, // Signal not available in signal map
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = LP_U0DSR_GPIO_NUM,
.iomux_func = LP_U0DSR_MUX_FUNC,
.input = 1,
.signal = UINT8_MAX, // Signal not available in signal map
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
},

19
components/soc/esp32c61/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,24 +8,27 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 10
#define U0TXD_GPIO_NUM 11
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define U2RXD_GPIO_NUM (-1)
#define U2TXD_GPIO_NUM (-1)
#define U2RTS_GPIO_NUM (-1)
#define U2CTS_GPIO_NUM (-1)
#define U2DTR_GPIO_NUM (-1)
#define U2DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -34,13 +37,21 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
/* Same goes for UART2 */
#define U2TXD_MUX_FUNC (-1)
#define U2RXD_MUX_FUNC (-1)
#define U2RTS_MUX_FUNC (-1)
#define U2CTS_MUX_FUNC (-1)
#define U2DTR_MUX_FUNC (-1)
#define U2DSR_MUX_FUNC (-1)

70
components/soc/esp32c61/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -14,33 +14,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
@@ -48,66 +62,94 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
{
// HP UART2
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = U2TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = U2RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = U2RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = U2CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U2DTR_GPIO_NUM,
.iomux_func = U2DTR_MUX_FUNC,
.input = 0,
.signal = U2DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U2DSR_GPIO_NUM,
.iomux_func = U2DSR_MUX_FUNC,
.input = 1,
.signal = U2DSR_IN_IDX,
},
},
.irq = ETS_UART2_INTR_SOURCE,
},

15
components/soc/esp32h2/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,20 +8,20 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 23
#define U0TXD_GPIO_NUM 24
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -30,8 +30,13 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)

48
components/soc/esp32h2/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2020-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2020-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -13,66 +13,94 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},

15
components/soc/esp32h21/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2024-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,20 +8,20 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 15
#define U0TXD_GPIO_NUM 16
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -30,8 +30,13 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)

46
components/soc/esp32h21/uart_periph.c
View File

@@ -13,66 +13,94 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},

12
components/soc/esp32h4/include/soc/uart_pins.h
View File

@@ -8,19 +8,20 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 23
#define U0TXD_GPIO_NUM 24
#define U0RTS_GPIO_NUM (-1)
#define U0CTS_GPIO_NUM (-1)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (-1)
#define U1TXD_GPIO_NUM (-1)
#define U1RTS_GPIO_NUM (-1)
#define U1CTS_GPIO_NUM (-1)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 4
#define LP_U0TXD_GPIO_NUM 5
@@ -34,11 +35,16 @@
/* No func for the following pins, they shall not be used */
#define U0RTS_MUX_FUNC (-1)
#define U0CTS_MUX_FUNC (-1)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (-1)
#define U1RXD_MUX_FUNC (-1)
#define U1RTS_MUX_FUNC (-1)
#define U1CTS_MUX_FUNC (-1)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (1)
#define LP_U0RXD_MUX_FUNC (1)

46
components/soc/esp32h4/uart_periph.c
View File

@@ -14,33 +14,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
@@ -48,33 +62,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
}

29
components/soc/esp32p4/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,39 +8,48 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 38
#define U0TXD_GPIO_NUM 37
#define U0RTS_GPIO_NUM 8
#define U0CTS_GPIO_NUM 9
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM 11
#define U1TXD_GPIO_NUM 10
#define U1RTS_GPIO_NUM 12
#define U1CTS_GPIO_NUM 13
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define U2RXD_GPIO_NUM (-1)
#define U2TXD_GPIO_NUM (-1)
#define U2RTS_GPIO_NUM (-1)
#define U2CTS_GPIO_NUM (-1)
#define U2DTR_GPIO_NUM (-1)
#define U2DSR_GPIO_NUM (-1)
#define U3RXD_GPIO_NUM (-1)
#define U3TXD_GPIO_NUM (-1)
#define U3RTS_GPIO_NUM (-1)
#define U3CTS_GPIO_NUM (-1)
#define U3DTR_GPIO_NUM (-1)
#define U3DSR_GPIO_NUM (-1)
#define U4RXD_GPIO_NUM (-1)
#define U4TXD_GPIO_NUM (-1)
#define U4RTS_GPIO_NUM (-1)
#define U4CTS_GPIO_NUM (-1)
#define U4DTR_GPIO_NUM (-1)
#define U4DSR_GPIO_NUM (-1)
#define LP_U0RXD_GPIO_NUM 15
#define LP_U0TXD_GPIO_NUM 14
#define LP_U0RTS_GPIO_NUM (-1)
#define LP_U0CTS_GPIO_NUM (-1)
#define LP_U0DTR_GPIO_NUM (-1)
#define LP_U0DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -48,30 +57,42 @@
#define U0RXD_MUX_FUNC (FUNC_GPIO38_UART0_RXD_PAD)
#define U0RTS_MUX_FUNC (FUNC_GPIO8_UART0_RTS_PAD)
#define U0CTS_MUX_FUNC (FUNC_GPIO9_UART0_CTS_PAD)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
/* Same goes for UART1 */
#define U1TXD_MUX_FUNC (FUNC_GPIO10_UART1_TXD_PAD)
#define U1RXD_MUX_FUNC (FUNC_GPIO11_UART1_RXD_PAD)
#define U1RTS_MUX_FUNC (FUNC_GPIO12_UART1_RTS_PAD)
#define U1CTS_MUX_FUNC (FUNC_GPIO13_UART1_CTS_PAD)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
/* No func for the following pins, they shall not be used */
#define U2TXD_MUX_FUNC (-1)
#define U2RXD_MUX_FUNC (-1)
#define U2RTS_MUX_FUNC (-1)
#define U2CTS_MUX_FUNC (-1)
#define U2DTR_MUX_FUNC (-1)
#define U2DSR_MUX_FUNC (-1)
#define U3TXD_MUX_FUNC (-1)
#define U3RXD_MUX_FUNC (-1)
#define U3RTS_MUX_FUNC (-1)
#define U3CTS_MUX_FUNC (-1)
#define U3DTR_MUX_FUNC (-1)
#define U3DSR_MUX_FUNC (-1)
#define U4TXD_MUX_FUNC (-1)
#define U4RXD_MUX_FUNC (-1)
#define U4RTS_MUX_FUNC (-1)
#define U4CTS_MUX_FUNC (-1)
#define U4DTR_MUX_FUNC (-1)
#define U4DSR_MUX_FUNC (-1)
#define LP_U0TXD_MUX_FUNC (0)
#define LP_U0RXD_MUX_FUNC (0)
#define LP_U0RTS_MUX_FUNC (-1)
#define LP_U0CTS_MUX_FUNC (-1)
#define LP_U0DTR_MUX_FUNC (-1)
#define LP_U0DSR_MUX_FUNC (-1)

136
components/soc/esp32p4/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -15,33 +15,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = UART0_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = UART0_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = UART0_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = UART0_CTS_PAD_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = UART0_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = UART0_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
@@ -49,33 +63,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART1
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = UART1_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = UART1_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = UART1_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = UART1_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = UART1_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = UART1_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
@@ -83,33 +111,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART2
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = UART2_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = UART2_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = UART2_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = UART2_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U2DTR_GPIO_NUM,
.iomux_func = U2DTR_MUX_FUNC,
.input = 0,
.signal = UART2_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U2DSR_GPIO_NUM,
.iomux_func = U2DSR_MUX_FUNC,
.input = 1,
.signal = UART2_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART2_INTR_SOURCE,
},
@@ -117,33 +159,47 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART3
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U3TXD_GPIO_NUM,
.iomux_func = U3TXD_MUX_FUNC,
.input = 0,
.signal = UART3_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U3RXD_GPIO_NUM,
.iomux_func = U3RXD_MUX_FUNC,
.input = 1,
.signal = UART3_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U3RTS_GPIO_NUM,
.iomux_func = U3RTS_MUX_FUNC,
.input = 0,
.signal = UART3_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U3CTS_GPIO_NUM,
.iomux_func = U3CTS_MUX_FUNC,
.input = 1,
.signal = UART3_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U3DTR_GPIO_NUM,
.iomux_func = U3DTR_MUX_FUNC,
.input = 0,
.signal = UART3_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U3DSR_GPIO_NUM,
.iomux_func = U3DSR_MUX_FUNC,
.input = 1,
.signal = UART3_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART3_INTR_SOURCE,
},
@@ -151,66 +207,94 @@ const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
// HP UART4
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U4TXD_GPIO_NUM,
.iomux_func = U4TXD_MUX_FUNC,
.input = 0,
.signal = UART4_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U4RXD_GPIO_NUM,
.iomux_func = U4RXD_MUX_FUNC,
.input = 1,
.signal = UART4_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U4RTS_GPIO_NUM,
.iomux_func = U4RTS_MUX_FUNC,
.input = 0,
.signal = UART4_RTS_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U4CTS_GPIO_NUM,
.iomux_func = U4CTS_MUX_FUNC,
.input = 1,
.signal = UART4_CTS_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U4DTR_GPIO_NUM,
.iomux_func = U4DTR_MUX_FUNC,
.input = 0,
.signal = UART4_DTR_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U4DSR_GPIO_NUM,
.iomux_func = U4DSR_MUX_FUNC,
.input = 1,
.signal = UART4_DSR_PAD_IN_IDX,
},
},
.irq = ETS_UART4_INTR_SOURCE,
},
{
// LP UART0
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = LP_U0TXD_GPIO_NUM,
.iomux_func = LP_U0TXD_MUX_FUNC,
.input = 0,
.signal = LP_UART_TXD_PAD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = LP_U0RXD_GPIO_NUM,
.iomux_func = LP_U0RXD_MUX_FUNC,
.input = 1,
.signal = LP_UART_RXD_PAD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = LP_U0RTS_GPIO_NUM,
.iomux_func = LP_U0RTS_MUX_FUNC,
.input = 0,
.signal = LP_UART_RTSN_PAD_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = LP_U0CTS_GPIO_NUM,
.iomux_func = LP_U0CTS_MUX_FUNC,
.input = 1,
.signal = LP_UART_CTSN_PAD_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = LP_U0DTR_GPIO_NUM,
.iomux_func = LP_U0DTR_MUX_FUNC,
.input = 0,
.signal = LP_UART_DTRN_PAD_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = LP_U0DSR_GPIO_NUM,
.iomux_func = LP_U0DSR_MUX_FUNC,
.input = 1,
.signal = LP_UART_DSRN_PAD_IN_IDX,
},
},
.irq = ETS_LP_UART_INTR_SOURCE,
},

13
components/soc/esp32s2/include/soc/uart_pins.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -8,19 +8,20 @@
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM (44)
#define U0TXD_GPIO_NUM (43)
#define U0RTS_GPIO_NUM (15)
#define U0CTS_GPIO_NUM (16)
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM (18)
#define U1TXD_GPIO_NUM (17)
#define U1RTS_GPIO_NUM (19)
#define U1CTS_GPIO_NUM (20)
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -28,8 +29,12 @@
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
#define U0RTS_MUX_FUNC (FUNC_XTAL_32K_P_U0RTS)
#define U0CTS_MUX_FUNC (FUNC_XTAL_32K_N_U0CTS)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
#define U1TXD_MUX_FUNC (FUNC_DAC_1_U1TXD)
#define U1RXD_MUX_FUNC (FUNC_DAC_2_U1RXD)
#define U1RTS_MUX_FUNC (FUNC_GPIO19_U1RTS)
#define U1CTS_MUX_FUNC (FUNC_GPIO20_U1CTS)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)

48
components/soc/esp32s2/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,66 +12,94 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},

33
components/soc/esp32s3/include/soc/uart_pins.h
View File

@@ -1,39 +1,34 @@
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
//
// Licensed under the Apache License, Version 2.0 (the "License");
// you may not use this file except in compliance with the License.
// You may obtain a copy of the License at
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
/*
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#pragma once
#include "soc/io_mux_reg.h"
/* Specify the number of pins for UART */
#define SOC_UART_PINS_COUNT (4)
/* Specify the GPIO pin number for each UART signal in the IOMUX */
#define U0RXD_GPIO_NUM 44
#define U0TXD_GPIO_NUM 43
#define U0CTS_GPIO_NUM 16
#define U0RTS_GPIO_NUM 15
#define U0DTR_GPIO_NUM (-1)
#define U0DSR_GPIO_NUM (-1)
#define U1RXD_GPIO_NUM 18
#define U1TXD_GPIO_NUM 17
#define U1CTS_GPIO_NUM 20
#define U1RTS_GPIO_NUM 19
#define U1DTR_GPIO_NUM (-1)
#define U1DSR_GPIO_NUM (-1)
#define U2RXD_GPIO_NUM (-1)
#define U2TXD_GPIO_NUM (-1)
#define U2CTS_GPIO_NUM (-1)
#define U2RTS_GPIO_NUM (-1)
#define U2DTR_GPIO_NUM (-1)
#define U2DSR_GPIO_NUM (-1)
/* The following defines are necessary for reconfiguring the UART
* to use IOMUX, at runtime. */
@@ -41,11 +36,15 @@
#define U0RXD_MUX_FUNC (FUNC_U0RXD_U0RXD)
#define U0RTS_MUX_FUNC (FUNC_XTAL_32K_P_U0RTS)
#define U0CTS_MUX_FUNC (FUNC_XTAL_32K_N_U0CTS)
#define U0DTR_MUX_FUNC (-1)
#define U0DSR_MUX_FUNC (-1)
#define U1TXD_MUX_FUNC (FUNC_DAC_1_U1TXD)
#define U1RXD_MUX_FUNC (FUNC_DAC_2_U1RXD)
#define U1RTS_MUX_FUNC (FUNC_GPIO19_U1RTS)
#define U1CTS_MUX_FUNC (FUNC_GPIO20_U1CTS)
#define U1DTR_MUX_FUNC (-1)
#define U1DSR_MUX_FUNC (-1)
/* UART2 cannot be used directly through the IOMUX, these value
* shall not be used. */
@@ -53,3 +52,5 @@
#define U2RXD_MUX_FUNC (-1)
#define U2RTS_MUX_FUNC (-1)
#define U2CTS_MUX_FUNC (-1)
#define U2DTR_MUX_FUNC (-1)
#define U2DSR_MUX_FUNC (-1)

72
components/soc/esp32s3/uart_periph.c
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -12,99 +12,141 @@
const uart_signal_conn_t uart_periph_signal[SOC_UART_NUM] = {
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U0TXD_GPIO_NUM,
.iomux_func = U0TXD_MUX_FUNC,
.input = 0,
.signal = U0TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U0RXD_GPIO_NUM,
.iomux_func = U0RXD_MUX_FUNC,
.input = 1,
.signal = U0RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U0RTS_GPIO_NUM,
.iomux_func = U0RTS_MUX_FUNC,
.input = 0,
.signal = U0RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U0CTS_GPIO_NUM,
.iomux_func = U0CTS_MUX_FUNC,
.input = 1,
.signal = U0CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U0DTR_GPIO_NUM,
.iomux_func = U0DTR_MUX_FUNC,
.input = 0,
.signal = U0DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U0DSR_GPIO_NUM,
.iomux_func = U0DSR_MUX_FUNC,
.input = 1,
.signal = U0DSR_IN_IDX,
},
},
.irq = ETS_UART0_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U1TXD_GPIO_NUM,
.iomux_func = U1TXD_MUX_FUNC,
.input = 0,
.signal = U1TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U1RXD_GPIO_NUM,
.iomux_func = U1RXD_MUX_FUNC,
.input = 1,
.signal = U1RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U1RTS_GPIO_NUM,
.iomux_func = U1RTS_MUX_FUNC,
.input = 0,
.signal = U1RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U1CTS_GPIO_NUM,
.iomux_func = U1CTS_MUX_FUNC,
.input = 1,
.signal = U1CTS_IN_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U1DTR_GPIO_NUM,
.iomux_func = U1DTR_MUX_FUNC,
.input = 0,
.signal = U1DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U1DSR_GPIO_NUM,
.iomux_func = U1DSR_MUX_FUNC,
.input = 1,
.signal = U1DSR_IN_IDX,
},
},
.irq = ETS_UART1_INTR_SOURCE,
},
{
.pins = {
[SOC_UART_TX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_TX] = {
.default_gpio = U2TXD_GPIO_NUM,
.iomux_func = U2TXD_MUX_FUNC,
.input = 0,
.signal = U2TXD_OUT_IDX,
},
[SOC_UART_RX_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RX] = {
.default_gpio = U2RXD_GPIO_NUM,
.iomux_func = U2RXD_MUX_FUNC,
.input = 1,
.signal = U2RXD_IN_IDX,
},
[SOC_UART_RTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_RTS] = {
.default_gpio = U2RTS_GPIO_NUM,
.iomux_func = U2RTS_MUX_FUNC,
.input = 0,
.signal = U2RTS_OUT_IDX,
},
[SOC_UART_CTS_PIN_IDX] = {
[SOC_UART_PERIPH_SIGNAL_CTS] = {
.default_gpio = U2CTS_GPIO_NUM,
.iomux_func = U2CTS_MUX_FUNC,
.input = 1,
.signal = U2CTS_IN_IDX,
}
},
[SOC_UART_PERIPH_SIGNAL_DTR] = {
.default_gpio = U2DTR_GPIO_NUM,
.iomux_func = U2DTR_MUX_FUNC,
.input = 0,
.signal = U2DTR_OUT_IDX,
},
[SOC_UART_PERIPH_SIGNAL_DSR] = {
.default_gpio = U2DSR_GPIO_NUM,
.iomux_func = U2DSR_MUX_FUNC,
.input = 1,
.signal = U2DSR_IN_IDX,
},
},
.irq = ETS_UART2_INTR_SOURCE,
}

17
components/soc/include/soc/uart_periph.h
View File

@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2019-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2019-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -21,10 +21,15 @@
extern "C" {
#endif
#define SOC_UART_TX_PIN_IDX (0)
#define SOC_UART_RX_PIN_IDX (1)
#define SOC_UART_RTS_PIN_IDX (2)
#define SOC_UART_CTS_PIN_IDX (3)
typedef enum {
SOC_UART_PERIPH_SIGNAL_TX = 0, /* Transmit signal*/
SOC_UART_PERIPH_SIGNAL_RX = 1, /* Receive signal*/
SOC_UART_PERIPH_SIGNAL_RTS = 2, /* Request to send signal (0 indicates allowing the other end to send data)*/
SOC_UART_PERIPH_SIGNAL_CTS = 3, /* Clear to send signal (0 indicates I am allowed to send data)*/
SOC_UART_PERIPH_SIGNAL_DTR = 4, /* Data terminal ready signal (1 indicates I am ready to transmit data)*/
SOC_UART_PERIPH_SIGNAL_DSR = 5, /* Data set ready signal (1 indicates the other end is ready to transmit data)*/
SOC_UART_PERIPH_SIGNAL_MAX,
} soc_uart_periph_signal_t;
/**
* @brief Macro that can be used to retrieve the signal of a certain pin for a
@@ -47,7 +52,7 @@ typedef struct {
} uart_periph_sig_t;
typedef struct {
const uart_periph_sig_t pins[SOC_UART_PINS_COUNT];
const uart_periph_sig_t pins[SOC_UART_PERIPH_SIGNAL_MAX];
const uint8_t irq;
} uart_signal_conn_t;

16
components/ulp/lp_core/lp_core_uart.c
View File

@@ -130,10 +130,10 @@ static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg)
#if !SOC_LP_GPIO_MATRIX_SUPPORTED
const uart_periph_sig_t *pins = uart_periph_signal[LP_UART_PORT_NUM].pins;
// LP_UART has its fixed IOs
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.tx_io_num < 0 || (cfg->uart_pin_cfg.tx_io_num == pins[SOC_UART_TX_PIN_IDX].default_gpio)), ESP_FAIL, LP_UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.rx_io_num < 0 || (cfg->uart_pin_cfg.rx_io_num == pins[SOC_UART_RX_PIN_IDX].default_gpio)), ESP_FAIL, LP_UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.rts_io_num < 0 || (cfg->uart_pin_cfg.rts_io_num == pins[SOC_UART_RTS_PIN_IDX].default_gpio)), ESP_FAIL, LP_UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.cts_io_num < 0 || (cfg->uart_pin_cfg.cts_io_num == pins[SOC_UART_CTS_PIN_IDX].default_gpio)), ESP_FAIL, LP_UART_TAG, "cts_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.tx_io_num < 0 || (cfg->uart_pin_cfg.tx_io_num == pins[SOC_UART_PERIPH_SIGNAL_TX].default_gpio)), ESP_FAIL, LP_UART_TAG, "tx_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.rx_io_num < 0 || (cfg->uart_pin_cfg.rx_io_num == pins[SOC_UART_PERIPH_SIGNAL_RX].default_gpio)), ESP_FAIL, LP_UART_TAG, "rx_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.rts_io_num < 0 || (cfg->uart_pin_cfg.rts_io_num == pins[SOC_UART_PERIPH_SIGNAL_RTS].default_gpio)), ESP_FAIL, LP_UART_TAG, "rts_io_num error");
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.cts_io_num < 0 || (cfg->uart_pin_cfg.cts_io_num == pins[SOC_UART_PERIPH_SIGNAL_CTS].default_gpio)), ESP_FAIL, LP_UART_TAG, "cts_io_num error");
#else
// LP_UART signals can be routed to any LP_IOs
ESP_RETURN_ON_FALSE((cfg->uart_pin_cfg.tx_io_num < 0 || rtc_gpio_is_valid_gpio(cfg->uart_pin_cfg.tx_io_num)), ESP_FAIL, LP_UART_TAG, "tx_io_num error");
@@ -143,13 +143,13 @@ static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg)
#endif /* SOC_LP_GPIO_MATRIX_SUPPORTED */
/* Configure Tx Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_TX_PIN_IDX);
ret = lp_uart_config_io(cfg->uart_pin_cfg.tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_PERIPH_SIGNAL_TX);
/* Configure Rx Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.rx_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_RX_PIN_IDX);
ret = lp_uart_config_io(cfg->uart_pin_cfg.rx_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_PERIPH_SIGNAL_RX);
/* Configure RTS Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_RTS_PIN_IDX);
ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY, SOC_UART_PERIPH_SIGNAL_RTS);
/* Configure CTS Pin */
ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_CTS_PIN_IDX);
ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY, SOC_UART_PERIPH_SIGNAL_CTS);
return ret;
}

20
docs/en/api-reference/peripherals/uart.rst
View File

@@ -139,14 +139,14 @@ Each of the above functions has a ``_get_`` counterpart to check the currently s
Set Communication Pins
^^^^^^^^^^^^^^^^^^^^^^^^^^
After setting communication parameters, configure the physical GPIO pins to which the other UART device will be connected. For this, call the function :cpp:func:`uart_set_pin` and specify the GPIO pin numbers to which the driver should route the TX, RX, RTS, and CTS signals. If you want to keep a currently allocated pin number for a specific signal, pass the macro :c:macro:`UART_PIN_NO_CHANGE`.
After setting communication parameters, configure the physical GPIO pins to which the other UART device will be connected. For this, call the function :cpp:func:`uart_set_pin` and specify the GPIO pin numbers to which the driver should route the TX, RX, RTS, CTS, DTR, and DSR signals. If you want to keep a currently allocated pin number for a specific signal, pass the macro :c:macro:`UART_PIN_NO_CHANGE`.
The same macro :c:macro:`UART_PIN_NO_CHANGE` should be specified for pins that will not be used.
.. code-block:: c
// Set UART pins(TX: IO4, RX: IO5, RTS: IO18, CTS: IO19)
ESP_ERROR_CHECK(uart_set_pin({IDF_TARGET_UART_EXAMPLE_PORT}, 4, 5, 18, 19));
// Set UART pins(TX: IO4, RX: IO5, RTS: IO18, CTS: IO19, DTR: UNUSED, DSR: UNUSED)
ESP_ERROR_CHECK(uart_set_pin({IDF_TARGET_UART_EXAMPLE_PORT}, 4, 5, 18, 19, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE));
.. _uart-api-running-uart-communication:
@@ -327,11 +327,15 @@ The {IDF_TARGET_NAME}'s RS485 UART hardware can detect signal collisions during
The collision detection feature allows handling collisions when their interrupts are activated and triggered. The interrupts ``UART_RS485_FRM_ERR_INT`` and ``UART_RS485_PARITY_ERR_INT`` can be used with the collision detection feature to control frame errors and parity bit errors accordingly in RS485 mode. This functionality is supported in the UART driver and can be used by selecting the :cpp:enumerator:`UART_MODE_RS485_APP_CTRL` mode (see the function :cpp:func:`uart_set_mode`).
The collision detection feature can work with circuit A and circuit C (see Section `Interface Connection Options`_). In the case of using circuit A or B, the RTS pin connected to the DE pin of the bus driver should be controlled by the user application. Use the function :cpp:func:`uart_get_collision_flag` to check if the collision detection flag has been raised.
The collision detection feature can work with circuit A and circuit C (see Section `Interface Connection Options`_). Use the function :cpp:func:`uart_get_collision_flag` to check if the collision detection flag has been raised. In the case of using circuit A or B, either DTR or RTS pin can be connected to the DE/~RE pin of the transceiver module to achieve half-duplex communication.
The {IDF_TARGET_NAME} UART controllers themselves do not support half-duplex communication as they cannot provide automatic control of the RTS pin connected to the RE/DE input of RS485 bus driver. However, half-duplex communication can be achieved via software control of the RTS pin by the UART driver. This can be enabled by selecting the :cpp:enumerator:`UART_MODE_RS485_HALF_DUPLEX` mode when calling :cpp:func:`uart_set_mode`.
The RS485 half-duplex communication mode is supported by the UART driver and can be activated by selecting the :cpp:enumerator:`UART_MODE_RS485_HALF_DUPLEX` mode calling :cpp:func:`uart_set_mode`. The DTR line is automatically controlled by the hardware directly under RS485 half-duplex mode, while the RTS line is software-controlled by the UART driver. Once the host starts writing data to the TX FIFO buffer, the UART driver automatically asserts the RTS pin (logic 1); once the last bit of the data has been transmitted, the driver de-asserts the RTS pin (logic 0). To use this mode, the software would have to disable the hardware flow control function. Since the switching is made in the interrupt handler, comparing to DTR line, some latency is expected on RTS line.
Once the host starts writing data to the TX FIFO buffer, the UART driver automatically asserts the RTS pin (logic 1); once the last bit of the data has been transmitted, the driver de-asserts the RTS pin (logic 0). To use this mode, the software would have to disable the hardware flow control function. This mode works with all the used circuits shown below.
.. only:: esp32
.. note::
On {IDF_TARGET_NAME}, DTR signal is only available on UART0. For other UART ports, you can only connect RTS signal to the DE/~RE pin of the transceiver module.
Interface Connection Options
@@ -358,7 +362,7 @@ Circuit A: Collision Detection Circuit
| B|----------<> B
TXD ------>| D ADM483 |
ESP | | RS485 bus side
RTS ------>| DE |
DTR/RTS ------>| DE |
| A|----------<> A
+----| /RE |
| +-------x-------+
@@ -381,7 +385,7 @@ Circuit B: Manual Switching Transmitter/Receiver Without Collision Detection
| B|-----------<> B
TXD ------>| D ADM483 |
ESP | | RS485 bus side
RTS --+--->| DE |
DTR/RTS --+--->| DE |
| | A|-----------<> A
+----| /RE |
+-------x-------+

5
docs/en/migration-guides/release-6.x/6.0/peripherals.rst
View File

@@ -64,6 +64,11 @@ LEDC
- :cpp:enumerator:`soc_periph_ledc_clk_src_legacy_t::LEDC_USE_RTC8M_CLK` has been removed. Please use ``LEDC_USE_RC_FAST_CLK`` instead.
UART
----
``UART_FIFO_LEN`` macro has been removed. Please use ``UART_HW_FIFO_LEN`` instead.
I2C
---

20
docs/zh_CN/api-reference/peripherals/uart.rst
View File

@@ -139,14 +139,14 @@ UART 驱动程序函数通过 :cpp:type:`uart_port_t` 识别不同的 UART 控
设置通信管脚
^^^^^^^^^^^^^^^^^^^^^^^^^^
通信参数设置完成后，可以配置其他 UART 设备连接的 GPIO 管脚。调用函数 :cpp:func:`uart_set_pin`，指定配置 Tx、Rx、RTS 和 CTS 信号的 GPIO 管脚编号。如要为特定信号保留当前分配的管脚编号，可传递宏 :c:macro:`UART_PIN_NO_CHANGE`。
通信参数设置完成后，可以配置其他 UART 设备连接的 GPIO 管脚。调用函数 :cpp:func:`uart_set_pin`，指定配置 Tx、Rx、RTS、CTS、DTR 和 DSR 信号的 GPIO 管脚编号。如要为特定信号保留当前分配的管脚编号，可传递宏 :c:macro:`UART_PIN_NO_CHANGE`。
请为不使用的管脚都指定为宏 :c:macro:`UART_PIN_NO_CHANGE`。
.. code-block:: c
// Set UART pins(TX: IO4, RX: IO5, RTS: IO18, CTS: IO19)
ESP_ERROR_CHECK(uart_set_pin({IDF_TARGET_UART_EXAMPLE_PORT}, 4, 5, 18, 19));
// Set UART pins(TX: IO4, RX: IO5, RTS: IO18, CTS: IO19, DTR: UNUSED, DSR: UNUSED)
ESP_ERROR_CHECK(uart_set_pin({IDF_TARGET_UART_EXAMPLE_PORT}, 4, 5, 18, 19, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE));
.. _uart-api-running-uart-communication:
@@ -327,11 +327,15 @@ RS485 特定通信模式简介
冲突检测功能允许在激活和触发中断时处理冲突。中断 ``UART_RS485_FRM_ERR_INT`` 和 ``UART_RS485_PARITY_ERR_INT`` 可与冲突检测功能一起使用，在 RS485 模式下分别控制帧错误和奇偶校验位错误。UART 驱动程序支持此功能，通过选择 :cpp:enumerator:`UART_MODE_RS485_APP_CTRL` 模式可以使用（参考函数 :cpp:func:`uart_set_mode`）。
冲突检测功能可与电路 A 和电路 C 一起使用（参考章节 `接口连接选项`_）。在使用电路 A 或 B 时，连接到总线驱动 DE 管脚的 RTS 管脚应由用户应用程序控制。调用函数 :cpp:func:`uart_get_collision_flag` 能够查看是否触发冲突检测标志。
冲突检测功能可与电路 A 和电路 C 一起使用（参考章节 `接口连接选项`_）。调用函数 :cpp:func:`uart_get_collision_flag` 能够查看是否触发冲突检测标志。在使用电路 A 或 B 时，DTR 或 RTS 管脚可以连接到收发器芯片的 DE/~RE 管脚，以实现半双工通信。
{IDF_TARGET_NAME} UART 控制器本身不支持半双工通信，因其无法自动控制连接到 RS485 总线驱动 RE/DE 输入的 RTS 管脚。然而，半双工通信能够通过 UART 驱动程序对 RTS 管脚的软件控制来实现，调用 :cpp:func:`uart_set_mode` 并选择 :cpp:enumerator:`UART_MODE_RS485_HALF_DUPLEX` 模式能够启用这一功能。
UART 驱动支持通过向 :cpp:func:`uart_set_mode` 函数传入 :cpp:enumerator:`UART_MODE_RS485_HALF_DUPLEX` 来启用 RS485 半双工通信模式。DTR 信号在 RS485 模式下由硬件直接控制，而 RTS 信号由 UART 驱动程序控制。当主机开始向 Tx FIFO 缓冲区写入数据时，UART 驱动程序会自动置位 RTS 信号（逻辑 1）；最后一位数据传输完成后，驱动程序就会取消置位 RTS 信号（逻辑 0）。要使用此模式，软件必须禁用硬件流控功能。由于切换是在中断处理程序中进行的，因此 RTS 线上会相对 DTR 线有一定延迟。
主机开始向 Tx FIFO 缓冲区写入数据时，UART 驱动程序会自动置位 RTS 管脚（逻辑 1）；最后一位数据传输完成后，驱动程序就会取消置位 RTS 管脚（逻辑 0）。要使用此模式，软件必须禁用硬件流控功能。此模式适用于下文所有已用电路。
.. only:: esp32
.. note::
ESP32 的 DTR 信号仅在 UART0 上可用。对于其他 UART 端口，只能将 RTS 信号连接到收发器芯片的 DE/~RE 管脚。
接口连接选项
@@ -358,7 +362,7 @@ RS485 特定通信模式简介
| B|----------<> B
TXD ------>| D ADM483 |
ESP | | RS485 bus side
RTS ------>| DE |
DTR/RTS ------>| DE |
| A|----------<> A
+----| /RE |
| +-------x-------+
@@ -381,7 +385,7 @@ RS485 特定通信模式简介
| B|-----------<> B
TXD ------>| D ADM483 |
ESP | | RS485 bus side
RTS --+--->| DE |
DTR/RTS --+--->| DE |
| | A|-----------<> A
+----| /RE |
+-------x-------+

5
docs/zh_CN/migration-guides/release-6.x/6.0/peripherals.rst
View File

@@ -64,6 +64,11 @@ LEDC
- :cpp:enumerator:`soc_periph_ledc_clk_src_legacy_t::LEDC_USE_RTC8M_CLK` 已被移除。请使用 ``LEDC_USE_RC_FAST_CLK`` 代替。
UART
----
``UART_FIFO_LEN`` 已被移除。请使用 ``UART_HW_FIFO_LEN`` 代替。
I2C
---

24
examples/peripherals/uart/uart_echo_rs485/README.md
View File

@@ -24,25 +24,25 @@ The MAX483 line driver is used for example below but other similar chips can be
| B|---------------|B |
TXD ------>| DI MAX483 | \ / | MAX483 DI|<----- TXD
ESP32 BOARD | | RS-485 side | | SERIAL ADAPTER SIDE
RTS --+--->| DE | / \ | DE|---+
DTR(RTS) --+--->| DE | / \ | DE|---+
| | A|---------------|A | |
+----| /RE | | /RE|---+-- RTS
+----| /RE | | /RE|---+-- DTR(RTS)
+-------x-------+ +-------x-------+
| |
--- ---
```
#### Connect an external RS485 serial interface to an ESP32 board
Connect a USB-to-RS485 adapter to a computer, then connect the adapter's A/B output lines with the corresponding A/B output lines of the RS485 line driver connected to the ESP32 chip (see figure above).
#### Connect an external RS485 serial interface to an ESP development board
Connect a USB-to-RS485 adapter to a computer, then connect the adapter's A/B output lines with the corresponding A/B output lines of the RS485 line driver connected to the ESP chip (see figure above).
```
------------------------------------------------------------------------------------------------------------------------------
| UART Interface | #define | Default pin for ESP32 | Default pins for others | External RS485 Driver Pin |
| ----------------------|--------------------|-----------------------|---------------------------|---------------------------|
| Transmit Data (TxD) | CONFIG_MB_UART_TXD | GPIO23 | GPIO9 | DI |
| Receive Data (RxD) | CONFIG_MB_UART_RXD | GPIO22 | GPIO8 | RO |
| Request To Send (RTS) | CONFIG_MB_UART_RTS | GPIO18 | GPIO10 | ~RE/DE |
| Ground | n/a | GND | GND | GND |
------------------------------------------------------------------------------------------------------------------------------
----------------------------------------------------------------------------
| UART Interface | #define | External RS485 Driver Pin |
| ----------------------|----------------------|---------------------------|
| Transmit Data (TxD) | CONFIG_ECHO_UART_TXD | DI |
| Receive Data (RxD) | CONFIG_ECHO_UART_RXD | RO |
| DTR / RTS | CONFIG_RS485_DE | ~RE/DE |
| Ground | n/a | GND |
----------------------------------------------------------------------------
```
Note: Each target chip has different GPIO pins available for UART connection. Please refer to UART documentation for selected target for more information.

21
examples/peripherals/uart/uart_echo_rs485/main/Kconfig.projbuild
View File

@@ -19,31 +19,32 @@ menu "Echo RS485 Example Configuration"
help
UART communication speed.
config ECHO_UART_RXD
int "UART RXD pin number"
config ECHO_RS485_RX_IO
int "RS485 RXD pin number"
range ENV_GPIO_RANGE_MIN ENV_GPIO_IN_RANGE_MAX
default 22 if IDF_TARGET_ESP32
default 8 if !IDF_TARGET_ESP32
help
GPIO number for UART RX pin. See UART documentation for more information
GPIO number for RS485 RO pin. See UART documentation for more information
about available pin numbers for UART.
config ECHO_UART_TXD
int "UART TXD pin number"
config ECHO_RS485_TX_IO
int "RS485 TXD pin number"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 23 if IDF_TARGET_ESP32
default 9 if !IDF_TARGET_ESP32
help
GPIO number for UART TX pin. See UART documentation for more information
GPIO number for RS485 DI pin. See UART documentation for more information
about available pin numbers for UART.
config ECHO_UART_RTS
int "UART RTS pin number"
config ECHO_RS485_DIRECTION_IO
int "RS485 ~RE/DE pin number"
range ENV_GPIO_RANGE_MIN ENV_GPIO_OUT_RANGE_MAX
default 18 if IDF_TARGET_ESP32
default 10 if !IDF_TARGET_ESP32
default 13 if IDF_TARGET_ESP32C6 || IDF_TARGET_ESP32C61 || IDF_TARGET_ESP32H4
default 10
help
GPIO number for UART RTS pin. This pin is connected to
GPIO number for the pin to connected to
~RE/DE pin of RS485 transceiver to switch direction.
See UART documentation for more information about available pin
numbers for UART.

23
examples/peripherals/uart/uart_echo_rs485/main/rs485_example.c
View File

@@ -25,14 +25,17 @@
// Note: Some pins on target chip cannot be assigned for UART communication.
// Please refer to documentation for selected board and target to configure pins using Kconfig.
#define ECHO_TEST_TXD (CONFIG_ECHO_UART_TXD)
#define ECHO_TEST_RXD (CONFIG_ECHO_UART_RXD)
#define ECHO_TEST_TXD (CONFIG_ECHO_RS485_TX_IO)
#define ECHO_TEST_RXD (CONFIG_ECHO_RS485_RX_IO)
// RTS for RS485 Half-Duplex Mode manages DE/~RE
#define ECHO_TEST_RTS (CONFIG_ECHO_UART_RTS)
// CTS is not used in RS485 Half-Duplex Mode
#define ECHO_TEST_CTS (UART_PIN_NO_CHANGE)
// DTR for RS485 Half-Duplex Mode manages DE/~RE
// However, on ESP32 non-UART0 port, DTR signal does not exist, so we use RTS instead
// RTS is managed by the software inside the driver, while DTR is controlled by the hardware directly, which eliminates latency
#if CONFIG_IDF_TARGET_ESP32
#define ECHO_TEST_RTS (CONFIG_ECHO_RS485_DIRECTION_IO)
#else
#define ECHO_TEST_DTR (CONFIG_ECHO_RS485_DIRECTION_IO)
#endif
#define BUF_SIZE (127)
#define BAUD_RATE (CONFIG_ECHO_UART_BAUD_RATE)
@@ -84,7 +87,11 @@ static void echo_task(void *arg)
ESP_LOGI(TAG, "UART set pins, mode and install driver.");
// Set UART pins as per KConfig settings
ESP_ERROR_CHECK(uart_set_pin(uart_num, ECHO_TEST_TXD, ECHO_TEST_RXD, ECHO_TEST_RTS, ECHO_TEST_CTS));
#if CONFIG_IDF_TARGET_ESP32
ESP_ERROR_CHECK(uart_set_pin(uart_num, ECHO_TEST_TXD, ECHO_TEST_RXD, ECHO_TEST_RTS, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE));
#else
ESP_ERROR_CHECK(uart_set_pin(uart_num, ECHO_TEST_TXD, ECHO_TEST_RXD, UART_PIN_NO_CHANGE, UART_PIN_NO_CHANGE, ECHO_TEST_DTR, UART_PIN_NO_CHANGE));
#endif
// Set RS485 half duplex mode
ESP_ERROR_CHECK(uart_set_mode(uart_num, UART_MODE_RS485_HALF_DUPLEX));

12
examples/peripherals/uart/uart_repl/main/uart_repl_example_main.c
View File

@@ -43,11 +43,11 @@ const char test_message[] = "This is an example string, if you can read this, th
*/
static void connect_uarts(void)
{
esp_rom_gpio_connect_out_signal(DEFAULT_UART_RX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_TX_PIN_IDX), false, false);
esp_rom_gpio_connect_in_signal(DEFAULT_UART_RX_PIN, UART_PERIPH_SIGNAL(0, SOC_UART_RX_PIN_IDX), false);
esp_rom_gpio_connect_out_signal(DEFAULT_UART_RX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_PERIPH_SIGNAL_TX), false, false);
esp_rom_gpio_connect_in_signal(DEFAULT_UART_RX_PIN, UART_PERIPH_SIGNAL(0, SOC_UART_PERIPH_SIGNAL_RX), false);
esp_rom_gpio_connect_out_signal(DEFAULT_UART_TX_PIN, UART_PERIPH_SIGNAL(0, SOC_UART_TX_PIN_IDX), false, false);
esp_rom_gpio_connect_in_signal(DEFAULT_UART_TX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_RX_PIN_IDX), false);
esp_rom_gpio_connect_out_signal(DEFAULT_UART_TX_PIN, UART_PERIPH_SIGNAL(0, SOC_UART_PERIPH_SIGNAL_TX), false, false);
esp_rom_gpio_connect_in_signal(DEFAULT_UART_TX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_PERIPH_SIGNAL_RX), false);
}
/**
@@ -58,8 +58,8 @@ static void connect_uarts(void)
*/
static void disconnect_uarts(void)
{
esp_rom_gpio_connect_out_signal(CONSOLE_UART_TX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_TX_PIN_IDX), false, false);
esp_rom_gpio_connect_in_signal(CONSOLE_UART_RX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_RX_PIN_IDX), false);
esp_rom_gpio_connect_out_signal(CONSOLE_UART_TX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_PERIPH_SIGNAL_TX), false, false);
esp_rom_gpio_connect_in_signal(CONSOLE_UART_RX_PIN, UART_PERIPH_SIGNAL(1, SOC_UART_PERIPH_SIGNAL_RX), false);
}
/**