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Merge branch 'bugfix/uart_8_16_bit_access_v5.1' into 'release/v5.1'

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fix(uart): fix 8/16-bit uart register access (v5.1)

See merge request espressif/esp-idf!35964
This commit is contained in:
morris
2024-12-27 10:19:46 +08:00
parent e7303ce35d 6888440994
commit 8722c3d4e7
2 changed files with 18 additions and 18 deletions
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18
components/hal/esp32c6/include/hal/uart_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -366,7 +366,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
*/ */
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{ {
return hw->status.rxfifo_cnt; return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
} }
/** /**
@@ -378,7 +378,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
*/ */
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{ {
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
} }
/** /**
@@ -453,7 +453,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
*/ */
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
{ {
hw->conf1.rxfifo_full_thrhd = full_thrhd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd);
} }
/** /**
@@ -467,7 +467,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
*/ */
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
{ {
hw->conf1.txfifo_empty_thrhd = empty_thrhd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd);
} }
/** /**
@@ -531,7 +531,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
{ {
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs);
hw->hwfc_conf_sync.rx_flow_en = 1; hw->hwfc_conf_sync.rx_flow_en = 1;
} else { } else {
hw->hwfc_conf_sync.rx_flow_en = 0; hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -577,8 +577,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
if (sw_flow_ctrl_en) { if (sw_flow_ctrl_en) {
hw->swfc_conf0_sync.xonoff_del = 1; hw->swfc_conf0_sync.xonoff_del = 1;
hw->swfc_conf0_sync.sw_flow_con_en = 1; hw->swfc_conf0_sync.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd);
hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
} else { } else {
@@ -843,7 +843,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
*/ */
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{ {
return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); return ((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) == 0) && (hw->fsm_status.st_utx_out == 0));
} }
/** /**

18
components/hal/esp32h2/include/hal/uart_ll.h
View File

@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -367,7 +367,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
*/ */
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw) FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{ {
return hw->status.rxfifo_cnt; return HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
} }
/** /**
@@ -379,7 +379,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
*/ */
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw) FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{ {
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt; return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
} }
/** /**
@@ -454,7 +454,7 @@ FORCE_INLINE_ATTR void uart_ll_get_parity(uart_dev_t *hw, uart_parity_t *parity_
*/ */
FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd) FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full_thrhd)
{ {
hw->conf1.rxfifo_full_thrhd = full_thrhd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, rxfifo_full_thrhd, full_thrhd);
} }
/** /**
@@ -468,7 +468,7 @@ FORCE_INLINE_ATTR void uart_ll_set_rxfifo_full_thr(uart_dev_t *hw, uint16_t full
*/ */
FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd) FORCE_INLINE_ATTR void uart_ll_set_txfifo_empty_thr(uart_dev_t *hw, uint16_t empty_thrhd)
{ {
hw->conf1.txfifo_empty_thrhd = empty_thrhd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->conf1, txfifo_empty_thrhd, empty_thrhd);
} }
/** /**
@@ -532,7 +532,7 @@ FORCE_INLINE_ATTR void uart_ll_set_hw_flow_ctrl(uart_dev_t *hw, uart_hw_flowcont
{ {
//only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set. //only when UART_HW_FLOWCTRL_RTS is set , will the rx_thresh value be set.
if (flow_ctrl & UART_HW_FLOWCTRL_RTS) { if (flow_ctrl & UART_HW_FLOWCTRL_RTS) {
hw->hwfc_conf_sync.rx_flow_thrhd = rx_thrs; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hwfc_conf_sync, rx_flow_thrhd, rx_thrs);
hw->hwfc_conf_sync.rx_flow_en = 1; hw->hwfc_conf_sync.rx_flow_en = 1;
} else { } else {
hw->hwfc_conf_sync.rx_flow_en = 0; hw->hwfc_conf_sync.rx_flow_en = 0;
@@ -578,8 +578,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
if (sw_flow_ctrl_en) { if (sw_flow_ctrl_en) {
hw->swfc_conf0_sync.xonoff_del = 1; hw->swfc_conf0_sync.xonoff_del = 1;
hw->swfc_conf0_sync.sw_flow_con_en = 1; hw->swfc_conf0_sync.sw_flow_con_en = 1;
hw->swfc_conf1.xon_threshold = flow_ctrl->xon_thrd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xon_threshold, flow_ctrl->xon_thrd);
hw->swfc_conf1.xoff_threshold = flow_ctrl->xoff_thrd; HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf1, xoff_threshold, flow_ctrl->xoff_thrd);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char); HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf0_sync, xoff_char, flow_ctrl->xoff_char);
} else { } else {
@@ -844,7 +844,7 @@ FORCE_INLINE_ATTR void uart_ll_get_data_bit_num(uart_dev_t *hw, uart_word_length
*/ */
FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw) FORCE_INLINE_ATTR bool uart_ll_is_tx_idle(uart_dev_t *hw)
{ {
return ((hw->status.txfifo_cnt == 0) && (hw->fsm_status.st_utx_out == 0)); return ((HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt) == 0) && (hw->fsm_status.st_utx_out == 0));
} }
/** /**