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https://github.com/espressif/esp-idf.git
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Merge branch 'feature/enable_flash_encryption_for_c5' into 'master'
feat: enable flash encryption support for c5 Closes IDF-8622 and IDF-9480 See merge request espressif/esp-idf!29578
This commit is contained in:
@@ -1,5 +1,5 @@
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/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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@@ -15,7 +15,7 @@
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#include <stdbool.h>
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#include <string.h>
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#include "soc/hp_system_reg.h"
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// #include "soc/xts_aes_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/soc.h"
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#include "soc/soc_caps.h"
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#include "hal/assert.h"
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@@ -27,7 +27,6 @@ extern "C" {
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/// Choose type of chip you want to encrypt manually
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typedef enum
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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FLASH_ENCRYPTION_MANU = 0, ///!< Manually encrypt the flash chip.
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PSRAM_ENCRYPTION_MANU = 1 ///!< Manually encrypt the psram chip.
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} flash_encrypt_ll_type_t;
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@@ -37,11 +36,15 @@ typedef enum
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*/
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static inline void spi_flash_encrypt_ll_enable(void)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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// HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
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// HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
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abort();
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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REG_SET_BIT(HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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HP_SYS_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
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HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT);
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#else
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REG_SET_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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HP_SYSTEM_ENABLE_DOWNLOAD_MANUAL_ENCRYPT |
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HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
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#endif
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}
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/*
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@@ -49,14 +52,17 @@ static inline void spi_flash_encrypt_ll_enable(void)
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*/
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static inline void spi_flash_encrypt_ll_disable(void)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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// HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
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abort();
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#if CONFIG_IDF_TARGET_ESP32C5_BETA3_VERSION
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REG_CLR_BIT(HP_SYS_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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HP_SYS_ENABLE_SPI_MANUAL_ENCRYPT);
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#else
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REG_CLR_BIT(HP_SYSTEM_EXTERNAL_DEVICE_ENCRYPT_DECRYPT_CONTROL_REG,
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HP_SYSTEM_ENABLE_SPI_MANUAL_ENCRYPT);
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#endif
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}
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/**
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* Choose type of chip you want to encrypt manully
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* Choose type of chip you want to encrypt manually
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*
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* @param type The type of chip to be encrypted
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*
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@@ -64,11 +70,9 @@ static inline void spi_flash_encrypt_ll_disable(void)
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*/
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static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// // Our hardware only support flash encryption
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// HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
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// REG_SET_FIELD(XTS_AES_DESTINATION_REG(0), XTS_AES_DESTINATION, type);
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abort();
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// Our hardware only support flash encryption
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HAL_ASSERT(type == FLASH_ENCRYPTION_MANU);
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REG_SET_FIELD(SPI_MEM_XTS_DESTINATION_REG(0), SPI_XTS_DESTINATION, type);
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}
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/**
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@@ -78,10 +82,8 @@ static inline void spi_flash_encrypt_ll_type(flash_encrypt_ll_type_t type)
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*/
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static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// // Desired block should not be larger than the block size.
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// REG_SET_FIELD(XTS_AES_LINESIZE_REG(0), XTS_AES_LINESIZE, size >> 5);
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abort();
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// Desired block should not be larger than the block size.
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REG_SET_FIELD(SPI_MEM_XTS_LINESIZE_REG(0), SPI_XTS_LINESIZE, size >> 5);
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}
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/**
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@@ -94,11 +96,9 @@ static inline void spi_flash_encrypt_ll_buffer_length(uint32_t size)
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*/
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static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const uint32_t* buffer, uint32_t size)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
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// HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
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// memcpy((void *)(XTS_AES_PLAIN_MEM(0) + plaintext_offs), buffer, size);
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abort();
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uint32_t plaintext_offs = (address % SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
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HAL_ASSERT(plaintext_offs + size <= SOC_FLASH_ENCRYPTED_XTS_AES_BLOCK_MAX);
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memcpy((void *)(SPI_MEM_XTS_PLAIN_BASE_REG(0) + plaintext_offs), buffer, size);
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}
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/**
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@@ -108,9 +108,7 @@ static inline void spi_flash_encrypt_ll_plaintext_save(uint32_t address, const u
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*/
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static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// REG_SET_FIELD(XTS_AES_PHYSICAL_ADDRESS_REG(0), XTS_AES_PHYSICAL_ADDRESS, flash_addr);
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abort();
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REG_SET_FIELD(SPI_MEM_XTS_PHYSICAL_ADDRESS_REG(0), SPI_XTS_PHYSICAL_ADDRESS, flash_addr);
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}
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/**
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@@ -118,9 +116,7 @@ static inline void spi_flash_encrypt_ll_address_save(uint32_t flash_addr)
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*/
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static inline void spi_flash_encrypt_ll_calculate_start(void)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// REG_SET_FIELD(XTS_AES_TRIGGER_REG(0), XTS_AES_TRIGGER, 1);
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abort();
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REG_SET_FIELD(SPI_MEM_XTS_TRIGGER_REG(0), SPI_XTS_TRIGGER, 1);
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}
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/**
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@@ -128,10 +124,8 @@ static inline void spi_flash_encrypt_ll_calculate_start(void)
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*/
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static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) == 0x1) {
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// }
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abort();
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while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) == 0x1) {
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}
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}
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/**
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@@ -139,11 +133,9 @@ static inline void spi_flash_encrypt_ll_calculate_wait_idle(void)
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*/
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static inline void spi_flash_encrypt_ll_done(void)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// REG_SET_BIT(XTS_AES_RELEASE_REG(0), XTS_AES_RELEASE);
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// while(REG_GET_FIELD(XTS_AES_STATE_REG(0), XTS_AES_STATE) != 0x3) {
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// }
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abort();
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REG_SET_BIT(SPI_MEM_XTS_RELEASE_REG(0), SPI_XTS_RELEASE);
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while(REG_GET_FIELD(SPI_MEM_XTS_STATE_REG(0), SPI_XTS_STATE) != 0x3) {
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}
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}
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/**
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@@ -151,9 +143,7 @@ static inline void spi_flash_encrypt_ll_done(void)
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*/
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static inline void spi_flash_encrypt_ll_destroy(void)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// REG_SET_BIT(XTS_AES_DESTROY_REG(0), XTS_AES_DESTROY);
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abort();
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REG_SET_BIT(SPI_MEM_XTS_DESTROY_REG(0), SPI_XTS_DESTROY);
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}
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/**
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@@ -164,10 +154,7 @@ static inline void spi_flash_encrypt_ll_destroy(void)
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*/
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static inline bool spi_flash_encrypt_ll_check(uint32_t address, uint32_t length)
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{
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// TODO: [ESP32C5] IDF-8622, IDF-8649
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// return ((address % length) == 0) ? true : false;
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abort();
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return (bool)0;
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return ((address % length) == 0) ? true : false;
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}
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#ifdef __cplusplus
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