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soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one
update all struct headers to be more "standardized": - bit fields are properly wrapped with struct - bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits - bit field should be uint32_t - typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199 added helper macros to force peripheral registers being accessed in 32 bitwidth added a check script into ci
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@@ -22,9 +22,11 @@ extern "C" {
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#endif
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#include <stdlib.h>
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#include "hal/misc.h"
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#include "hal/assert.h"
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#include "hal/timer_types.h"
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#include "soc/timer_periph.h"
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#include "soc/timer_group_struct.h"
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_Static_assert(TIMER_INTR_T0 == TIMG_T0_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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_Static_assert(TIMER_INTR_T1 == TIMG_T1_INT_CLR, "Add mapping to LL interrupt handling, since it's no longer naturally compatible with the timer_intr_t");
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@@ -50,7 +52,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
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}
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int timer_en = hw->hw_timer[timer_num].config.enable;
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hw->hw_timer[timer_num].config.enable = 0;
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hw->hw_timer[timer_num].config.divider = divider;
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HAL_FORCE_MODIFY_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider, divider);
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hw->hw_timer[timer_num].config.enable = timer_en;
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}
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@@ -65,7 +67,7 @@ static inline void timer_ll_set_divider(timg_dev_t *hw, timer_idx_t timer_num, u
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*/
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static inline void timer_ll_get_divider(timg_dev_t *hw, timer_idx_t timer_num, uint32_t *divider)
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{
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uint32_t d = hw->hw_timer[timer_num].config.divider;
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uint32_t d = HAL_FORCE_READ_U32_REG_FIELD(hw->hw_timer[timer_num].config, divider);
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if (d == 0) {
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d = 65536;
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} else if (d == 1) {
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