alex/esp-idf
1
0
Fork 0
mirror of https://github.com/espressif/esp-idf.git synced 2025-10-05 21:00:04 +00:00
Code Issues Packages Projects Releases Wiki Activity

soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one

Browse Source 
update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
This commit is contained in:
SalimTerryLi
2021-08-23 14:03:23 +08:00
parent ed8df94915
commit 874a720286
205 changed files with 1439 additions and 3252 deletions
Download Patch File Download Diff File Expand all files Collapse all files

27
components/hal/esp32/include/hal/uart_ll.h
View File

@@ -17,8 +17,11 @@
#pragma once
#include "hal/misc.h"
#include "esp_attr.h"
#include "soc/uart_periph.h"
#include "soc/uart_struct.h"
#include "hal/uart_types.h"
#ifdef __cplusplus
@@ -249,7 +252,7 @@ FORCE_INLINE_ATTR void uart_ll_rxfifo_rst(uart_dev_t *hw)
//Get the UART APB fifo addr
uint32_t fifo_addr = (hw == &UART0) ? UART_FIFO_REG(0) : (hw == &UART1) ? UART_FIFO_REG(1) : UART_FIFO_REG(2);
do {
fifo_cnt = hw->status.rxfifo_cnt;
fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
rxmem_sta.val = hw->mem_rx_status.val;
if(fifo_cnt != 0 || (rxmem_sta.rd_addr != rxmem_sta.wr_addr)) {
READ_PERI_REG(fifo_addr);
@@ -287,7 +290,7 @@ FORCE_INLINE_ATTR void uart_ll_txfifo_rst(uart_dev_t *hw)
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
{
uint32_t fifo_cnt = hw->status.rxfifo_cnt;
uint32_t fifo_cnt = HAL_FORCE_READ_U32_REG_FIELD(hw->status, rxfifo_cnt);
typeof(hw->mem_rx_status) rx_status = hw->mem_rx_status;
uint32_t len = 0;
@@ -313,7 +316,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_rxfifo_len(uart_dev_t *hw)
*/
FORCE_INLINE_ATTR uint32_t uart_ll_get_txfifo_len(uart_dev_t *hw)
{
return UART_LL_FIFO_DEF_LEN - hw->status.txfifo_cnt;
return UART_LL_FIFO_DEF_LEN - HAL_FORCE_READ_U32_REG_FIELD(hw->status, txfifo_cnt);
}
/**
@@ -453,7 +456,7 @@ FORCE_INLINE_ATTR void uart_ll_set_tx_idle_num(uart_dev_t *hw, uint32_t idle_num
FORCE_INLINE_ATTR void uart_ll_tx_break(uart_dev_t *hw, uint32_t break_num)
{
if(break_num > 0) {
hw->idle_conf.tx_brk_num = break_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->idle_conf, tx_brk_num, break_num);
hw->conf0.txd_brk = 1;
} else {
hw->conf0.txd_brk = 0;
@@ -518,10 +521,10 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
if(sw_flow_ctrl_en) {
hw->flow_conf.xonoff_del = 1;
hw->flow_conf.sw_flow_con_en = 1;
hw->swfc_conf.xon_threshold = flow_ctrl->xon_thrd;
hw->swfc_conf.xoff_threshold = flow_ctrl->xoff_thrd;
hw->swfc_conf.xon_char = flow_ctrl->xon_char;
hw->swfc_conf.xoff_char = flow_ctrl->xoff_char;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_threshold, flow_ctrl->xon_thrd);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_threshold, flow_ctrl->xoff_thrd);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xon_char, flow_ctrl->xon_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->swfc_conf, xoff_char, flow_ctrl->xoff_char);
} else {
hw->flow_conf.sw_flow_con_en = 0;
hw->flow_conf.xonoff_del = 0;
@@ -543,8 +546,8 @@ FORCE_INLINE_ATTR void uart_ll_set_sw_flow_ctrl(uart_dev_t *hw, uart_sw_flowctrl
*/
FORCE_INLINE_ATTR void uart_ll_set_at_cmd_char(uart_dev_t *hw, uart_at_cmd_t *cmd_char)
{
hw->at_cmd_char.data = cmd_char->cmd_char;
hw->at_cmd_char.char_num = cmd_char->char_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, data, cmd_char->cmd_char);
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->at_cmd_char, char_num, cmd_char->char_num);
hw->at_cmd_postcnt.post_idle_num = cmd_char->post_idle;
hw->at_cmd_precnt.pre_idle_num = cmd_char->pre_idle;
hw->at_cmd_gaptout.rx_gap_tout = cmd_char->gap_tout;
@@ -729,8 +732,8 @@ FORCE_INLINE_ATTR void uart_ll_set_mode(uart_dev_t *hw, uart_mode_t mode)
*/
FORCE_INLINE_ATTR void uart_ll_get_at_cmd_char(uart_dev_t *hw, uint8_t *cmd_char, uint8_t *char_num)
{
*cmd_char = hw->at_cmd_char.data;
*char_num = hw->at_cmd_char.char_num;
*cmd_char = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, data);
*char_num = HAL_FORCE_READ_U32_REG_FIELD(hw->at_cmd_char, char_num);
}
/**