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soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one

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update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
This commit is contained in:
SalimTerryLi
2021-08-23 14:03:23 +08:00
parent ed8df94915
commit 874a720286
205 changed files with 1439 additions and 3252 deletions
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15
components/hal/esp32h2/include/hal/adc_ll.h
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@@ -24,6 +24,7 @@
#include "soc/apb_saradc_reg.h"
#include "soc/rtc_cntl_struct.h"
#include "soc/rtc_cntl_reg.h"
#include "hal/misc.h"
#ifdef __cplusplus
extern "C" {
@@ -94,11 +95,11 @@ typedef enum {
static inline void adc_ll_digi_set_fsm_time(uint32_t rst_wait, uint32_t start_wait, uint32_t standby_wait)
{
// Internal FSM reset wait time
APB_SARADC.fsm_wait.rstb_wait = rst_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, rstb_wait, rst_wait);
// Internal FSM start wait time
APB_SARADC.fsm_wait.xpd_wait = start_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, xpd_wait, start_wait);
// Internal FSM standby wait time
APB_SARADC.fsm_wait.standby_wait = standby_wait;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.fsm_wait, standby_wait, standby_wait);
}
/**
@@ -124,7 +125,7 @@ static inline void adc_ll_set_sample_cycle(uint32_t sample_cycle)
static inline void adc_ll_digi_set_clk_div(uint32_t div)
{
/* ADC clock devided from digital controller clock clk */
APB_SARADC.ctrl.sar_clk_div = div;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl, sar_clk_div, div);
}
/**
@@ -135,7 +136,7 @@ static inline void adc_ll_digi_set_clk_div(uint32_t div)
*/
static inline void adc_ll_digi_set_convert_limit_num(uint32_t meas_num)
{
APB_SARADC.ctrl2.max_meas_num = meas_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.ctrl2, max_meas_num, meas_num);
}
/**
@@ -267,7 +268,7 @@ static inline void adc_ll_digi_trigger_disable(void)
*/
static inline void adc_ll_digi_controller_clk_div(uint32_t div_num, uint32_t div_b, uint32_t div_a)
{
APB_SARADC.apb_adc_clkm_conf.clkm_div_num = div_num;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.apb_adc_clkm_conf, clkm_div_num, div_num);
APB_SARADC.apb_adc_clkm_conf.clkm_div_b = div_b;
APB_SARADC.apb_adc_clkm_conf.clkm_div_a = div_a;
}
@@ -404,7 +405,7 @@ static inline void adc_ll_digi_monitor_disable(adc_digi_monitor_idx_t idx)
*/
static inline void adc_ll_digi_dma_set_eof_num(uint32_t num)
{
APB_SARADC.dma_conf.apb_adc_eof_num = num;
HAL_FORCE_MODIFY_U32_REG_FIELD(APB_SARADC.dma_conf, apb_adc_eof_num, num);
}
/**