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soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one

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update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci
This commit is contained in:
SalimTerryLi
2021-08-23 14:03:23 +08:00
parent ed8df94915
commit 874a720286
205 changed files with 1439 additions and 3252 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
components/soc/esp32s2/include/soc/apb_ctrl_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_ctrl_dev_s {
union {
struct {
uint32_t pre_div: 10;

2
components/soc/esp32s2/include/soc/apb_saradc_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct apb_saradc_dev_s {
union {
struct {
uint32_t start_force: 1;

6
components/soc/esp32s2/include/soc/cp_dma_struct.h
View File

@@ -69,6 +69,7 @@ typedef union {
* This is the interrupt raw bit. Triggered when crc calculation is done.
*/
uint32_t dma_crc_done_int_raw: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_raw_reg_t;
@@ -123,6 +124,7 @@ typedef union {
* cp_crc_done_int_ena is set to 1.
*/
uint32_t dma_crc_done_int_st: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_st_reg_t;
@@ -168,6 +170,7 @@ typedef union {
* This is the interrupt enable bit for cp_crc_done_int interrupt.
*/
uint32_t dma_crc_done_int_ena: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_ena_reg_t;
@@ -213,6 +216,7 @@ typedef union {
* Set this bit to clear cp_crc_done_int interrupt.
*/
uint32_t dma_crc_done_int_clr: 1;
uint32_t reserved9: 23;
};
uint32_t val;
} cp_dma_int_clr_reg_t;
@@ -491,6 +495,7 @@ typedef union {
* Copy DMA FIFO empty signal.
*/
uint32_t dma_fifo_empty: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} cp_dma_in_st_reg_t;
@@ -516,6 +521,7 @@ typedef union {
* Copy DMA FIFO full signal.
*/
uint32_t dma_fifo_full: 1;
uint32_t reserved24: 8;
};
uint32_t val;
} cp_dma_out_st_reg_t;

12
components/soc/esp32s2/include/soc/dedic_gpio_struct.h
View File

@@ -31,6 +31,7 @@ typedef union {
* gpio.
*/
uint32_t gpio_out_drt_vlaue: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_drt_reg_t;
@@ -49,6 +50,7 @@ typedef union {
* channel's output would be masked.
*/
uint32_t gpio_out_msk: 8;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_out_msk_reg_t;
@@ -98,6 +100,7 @@ typedef union {
* clear output value; 3: inverse output value.
*/
uint32_t gpio_out_idv_ch7: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_out_idv_reg_t;
@@ -147,6 +150,7 @@ typedef union {
* select CPU instructors.
*/
uint32_t gpio_out_cpu_sel7: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_cpu_reg_t;
@@ -196,6 +200,7 @@ typedef union {
* 3: three clock delay.
*/
uint32_t gpio_in_dly_ch7: 2;
uint32_t reserved16: 16;
};
uint32_t val;
} dedic_gpio_in_dly_reg_t;
@@ -285,6 +290,7 @@ typedef union {
* 6/7: falling and raising edge trigger.
*/
uint32_t gpio_intr_mode_ch7: 3;
uint32_t reserved24: 8;
};
uint32_t val;
} dedic_gpio_intr_rcgn_reg_t;
@@ -301,6 +307,7 @@ typedef union {
* DEDIC_GPIO_OUT_IDV_REG.
*/
uint32_t gpio_out_status: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_out_scan_reg_t;
@@ -314,6 +321,7 @@ typedef union {
* gpio in value after configured by DEDIC_GPIO_IN_DLY_REG.
*/
uint32_t gpio_in_status: 8;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_in_scan_reg_t;
@@ -365,6 +373,7 @@ typedef union {
* change configured by DEDIC_GPIO_INTR_RCGN_REG.
*/
uint32_t gpio7_int_raw: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_raw_reg_t;
@@ -406,6 +415,7 @@ typedef union {
* This enable bit for reg_gpio7_int_st register.
*/
uint32_t gpio7_int_ena: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_rls_reg_t;
@@ -447,6 +457,7 @@ typedef union {
* This is the status bit for reg_gpio7_int_raw when reg_gpio7_int_ena is set to 1.
*/
uint32_t gpio7_int_st: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_st_reg_t;
@@ -488,6 +499,7 @@ typedef union {
* Set this bit to clear the reg_gpio7_int_raw interrupt.
*/
uint32_t gpio7_int_clr: 1;
uint32_t reserved8: 24;
};
uint32_t val;
} dedic_gpio_intr_clr_reg_t;

2
components/soc/esp32s2/include/soc/efuse_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct efuse_dev_s {
uint32_t pgm_data0; /**/
union {
struct {

2
components/soc/esp32s2/include/soc/gpio_sd_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_sd_dev_s {
union {
struct {
uint32_t duty: 8;

2
components/soc/esp32s2/include/soc/gpio_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct gpio_dev_s {
uint32_t bt_select; /**/
uint32_t out; /**/
uint32_t out_w1ts; /**/

2
components/soc/esp32s2/include/soc/i2c_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2c_dev_s {
union {
struct {
uint32_t period: 14;

2
components/soc/esp32s2/include/soc/i2s_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct i2s_dev_s {
uint32_t reserved_0;
uint32_t reserved_4;
union {

2
components/soc/esp32s2/include/soc/ledc_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct ledc_dev_s {
struct {
struct {
union {

8
components/soc/esp32s2/include/soc/rmt_struct.h
View File

@@ -20,7 +20,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rmt_dev_s {
uint32_t data_ch[4]; /* Data FIFO, Can only be accessed by PeriBus2 */
struct {
union {
@@ -300,11 +300,9 @@ typedef struct {
} rmt_item32_t;
//Allow access to RMT memory using RMTMEM.chan[0].data32[8]
typedef volatile struct {
typedef volatile struct rmt_mem_s {
struct {
union {
rmt_item32_t data32[64];
};
rmt_item32_t data32[64];
} chan[4];
} rmt_mem_t;
extern rmt_mem_t RMTMEM;

2
components/soc/esp32s2/include/soc/rtc_cntl_struct.h
View File

@@ -19,7 +19,7 @@ extern "C" {
#include <stdint.h>
typedef volatile struct {
typedef volatile struct rtc_cntl_dev_s {
union {
struct {
uint32_t sw_stall_appcpu_c0: 2; /*{reg_sw_stall_appcpu_c1[5:0] reg_sw_stall_appcpu_c0[1:0]} == 0x86 will stall APP CPU*/

2
components/soc/esp32s2/include/soc/rtc_i2c_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_i2c_dev_s {
union {
struct {
uint32_t period: 20; /*time period that scl = 0*/

2
components/soc/esp32s2/include/soc/rtc_io_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct rtc_io_dev_s {
union {
struct {
uint32_t reserved0: 10;

2
components/soc/esp32s2/include/soc/sens_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct sens_dev_s {
union {
struct {
uint32_t sar1_clk_div: 8; /*clock divider*/

2
components/soc/esp32s2/include/soc/syscon_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct syscon_dev_s {
union {
struct {
uint32_t pre_div: 10;

4
components/soc/esp32s2/include/soc/systimer_struct.h
View File

@@ -91,6 +91,7 @@ typedef union {
* system timer accumulation step when using PLL
*/
uint32_t timer_pll_step: 10;
uint32_t reserved20: 12;
};
uint32_t val;
} systimer_step_reg_t;
@@ -201,6 +202,7 @@ typedef union {
* system timer target2 interrupt enable
*/
uint32_t systimer_int2_ena: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_ena_reg_t;
@@ -222,6 +224,7 @@ typedef union {
* system timer target2 interrupt raw
*/
uint32_t systimer_int2_raw: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_raw_reg_t;
@@ -243,6 +246,7 @@ typedef union {
* system timer target2 interrupt clear
*/
uint32_t systimer_int2_clr: 1;
uint32_t reserved3: 29;
};
uint32_t val;
} systimer_int_clr_reg_t;

86
components/soc/esp32s2/include/soc/twai_struct.h
View File

@@ -35,10 +35,10 @@ typedef volatile struct twai_dev_s {
uint32_t lom: 1; /* MOD.1 Listen Only Mode */
uint32_t stm: 1; /* MOD.2 Self Test Mode */
uint32_t afm: 1; /* MOD.3 Acceptance Filter Mode */
uint32_t reserved28: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
uint32_t reserved4: 28; /* Internal Reserved. MOD.4 Sleep Mode not supported */
};
uint32_t val;
} mode_reg; /* Address 0 */
} mode_reg; /* Address 0x0000 */
union {
struct {
uint32_t tr: 1; /* CMR.0 Transmission Request */
@@ -46,10 +46,10 @@ typedef volatile struct twai_dev_s {
uint32_t rrb: 1; /* CMR.2 Release Receive Buffer */
uint32_t cdo: 1; /* CMR.3 Clear Data Overrun */
uint32_t srr: 1; /* CMR.4 Self Reception Request */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} command_reg; /* Address 1 */
} command_reg; /* Address 0x0004 */
union {
struct {
uint32_t rbs: 1; /* SR.0 Receive Buffer Status */
@@ -61,37 +61,39 @@ typedef volatile struct twai_dev_s {
uint32_t es: 1; /* SR.6 Error Status */
uint32_t bs: 1; /* SR.7 Bus Status */
uint32_t ms: 1; /* SR.8 Miss Status */
uint32_t reserved23: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} status_reg; /* Address 2 */
} status_reg; /* Address 0x0008 */
union {
struct {
uint32_t ri: 1; /* IR.0 Receive Interrupt */
uint32_t ti: 1; /* IR.1 Transmit Interrupt */
uint32_t ei: 1; /* IR.2 Error Interrupt */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doi: 1; /* IR.3 Data Overrun Interrupt */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epi: 1; /* IR.5 Error Passive Interrupt */
uint32_t ali: 1; /* IR.6 Arbitration Lost Interrupt */
uint32_t bei: 1; /* IR.7 Bus Error Interrupt */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_reg; /* Address 3 */
} interrupt_reg; /* Address 0x000C */
union {
struct {
uint32_t rie: 1; /* IER.0 Receive Interrupt Enable */
uint32_t tie: 1; /* IER.1 Transmit Interrupt Enable */
uint32_t eie: 1; /* IER.2 Error Interrupt Enable */
uint32_t reserved2: 2; /* Internal Reserved (Data Overrun interrupt and Wake-up not supported) */
uint32_t doie: 1; /* IER.3 Data Overrun Interrupt Enable */
uint32_t reserved4: 1; /* Internal Reserved (Wake-up not supported) */
uint32_t epie: 1; /* IER.5 Error Passive Interrupt Enable */
uint32_t alie: 1; /* IER.6 Arbitration Lost Interrupt Enable */
uint32_t beie: 1; /* IER.7 Bus Error Interrupt Enable */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} interrupt_enable_reg; /* Address 4 */
uint32_t reserved_05; /* Address 5 */
} interrupt_enable_reg; /* Address 0x0010 */
uint32_t reserved_14;
union {
struct {
uint32_t brp: 14; /* BTR0[13:0] Baud Rate Prescaler */
@@ -99,58 +101,58 @@ typedef volatile struct twai_dev_s {
uint32_t reserved16: 16; /* Internal Reserved */
};
uint32_t val;
} bus_timing_0_reg; /* Address 6 */
} bus_timing_0_reg; /* Address 0x0018 */
union {
struct {
uint32_t tseg1: 4; /* BTR1[3:0] Timing Segment 1 */
uint32_t tseg2: 3; /* BTR1[6:4] Timing Segment 2 */
uint32_t sam: 1; /* BTR1.7 Sampling*/
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} bus_timing_1_reg; /* Address 7 */
uint32_t reserved_08; /* Address 8 (Output control not supported) */
uint32_t reserved_09; /* Address 9 (Test Register not supported) */
uint32_t reserved_10; /* Address 10 */
} bus_timing_1_reg; /* Address 0x001C */
uint32_t reserved_20; /* Address 0x0020 (Output control not supported) */
uint32_t reserved_24; /* Address 0x0024 (Test Register not supported) */
uint32_t reserved_28; /* Address 0x0028 */
//Capture and Counter Registers
union {
struct {
uint32_t alc: 5; /* ALC[4:0] Arbitration lost capture */
uint32_t reserved27: 27; /* Internal Reserved */
uint32_t reserved5: 27; /* Internal Reserved */
};
uint32_t val;
} arbitration_lost_captue_reg; /* Address 11 */
} arbitration_lost_captue_reg; /* Address 0x002C */
union {
struct {
uint32_t seg: 5; /* ECC[4:0] Error Code Segment 0 to 5 */
uint32_t dir: 1; /* ECC.5 Error Direction (TX/RX) */
uint32_t errc: 2; /* ECC[7:6] Error Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_code_capture_reg; /* Address 12 */
} error_code_capture_reg; /* Address 0x0030 */
union {
struct {
uint32_t ewl: 8; /* EWL[7:0] Error Warning Limit */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} error_warning_limit_reg; /* EWLR[7:0] Error Warning Limit: Address 13 */
} error_warning_limit_reg; /* Address 0x0034 */
union {
struct {
uint32_t rxerr: 8; /* RXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} rx_error_counter_reg; /* Address 12 */
} rx_error_counter_reg; /* Address 0x0038 */
union {
struct {
uint32_t txerr: 8; /* TXERR[7:0] Receive Error Counter */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} tx_error_counter_reg; /* Address 15 */
} tx_error_counter_reg; /* Address 0x003C */
//Shared Registers (TX Buff/RX Buff/Acc Filter)
union {
@@ -158,45 +160,49 @@ typedef volatile struct twai_dev_s {
union {
struct {
uint32_t byte: 8; /* ACRx[7:0] Acceptance Code */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} acr[4];
union {
struct {
uint32_t byte: 8; /* AMRx[7:0] Acceptance Mask */
uint32_t reserved24: 24; /* Internal Reserved */
uint32_t reserved8: 24; /* Internal Reserved */
};
uint32_t val;
} amr[4];
uint32_t reserved32[5];
uint32_t reserved_60;
uint32_t reserved_64;
uint32_t reserved_68;
uint32_t reserved_6c;
uint32_t reserved_70;
} acceptance_filter;
union {
struct {
uint32_t byte: 8;
uint32_t reserved24: 24;
uint32_t byte: 8; /* TX/RX Byte X [7:0] */
uint32_t reserved24: 24; /* Internal Reserved */
};
uint32_t val;
} tx_rx_buffer[13];
}; /* Address 16-28 TX/RX Buffer and Acc Filter*/;
}; /* Address 0x0040 - 0x0070 */
//Misc Registers
union {
struct {
uint32_t rmc: 7; /* RMC[6:0] RX Message Counter */
uint32_t reserved25: 25; /* Internal Reserved */
uint32_t reserved7: 25; /* Internal Reserved */
};
uint32_t val;
} rx_message_counter_reg; /* Address 29 */
uint32_t reserved_30; /* Address 30 (RX Buffer Start Address not supported) */
} rx_message_counter_reg; /* Address 0x0074 */
uint32_t reserved_78; /* Address 0x0078 (RX Buffer Start Address not supported) */
union {
struct {
uint32_t cd: 8; /* CDR[7:0] CLKOUT frequency selector based of fOSC */
uint32_t co: 1; /* CDR.8 CLKOUT enable/disable */
uint32_t reserved24: 23; /* Internal Reserved */
uint32_t reserved9: 23; /* Internal Reserved */
};
uint32_t val;
} clock_divider_reg; /* Address 31 */
} clock_divider_reg; /* Address 0x007C */
} twai_dev_t;
_Static_assert(sizeof(twai_dev_t) == 128, "TWAI registers should be 32 * 4 bytes");

2
components/soc/esp32s2/include/soc/uart_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uart_dev_s {
union {
struct {
uint32_t rw_byte;/*note: rw_byte is a uint8_t field, however, ESP32-S2 do not support 8 bits read/write*/

2
components/soc/esp32s2/include/soc/uhci_struct.h
View File

@@ -17,7 +17,7 @@
extern "C" {
#endif
typedef volatile struct {
typedef volatile struct uhci_dev_s {
union {
struct {
uint32_t in_rst: 1;

1
components/soc/esp32s2/include/soc/usb_wrap_struct.h
View File

@@ -153,6 +153,7 @@ typedef union {
* USB D- rx value in test.
*/
uint32_t test_rx_dm:1;
uint32_t reserved:25;
};
uint32_t val;
} usb_wrap_test_conf_reg_t;

2
components/soc/esp32s2/include/soc/usbh_struct.h
View File

@@ -830,7 +830,7 @@ typedef union {
uint32_t bbleerr: 1;
uint32_t nakintrpt: 1;
uint32_t nyetintrpt: 1;
uint32_t reserved16: 16;
uint32_t reserved15: 17;
};
uint32_t val;
} usb_diepint_reg_t;