soc/ll: workaround compiler bug that generate 8/16 bits inst instead of 32 bits one

update all struct headers to be more "standardized":

- bit fields are properly wrapped with struct
- bitwidth sum should be 32 within same struct, so that it's correctly padded with reserved bits
- bit field should be uint32_t
- typedef volatile struct xxx{} yyy;: xxx must exists. refer: https://github.com/espressif/esp-idf/pull/3199

added helper macros to force peripheral registers being accessed in 32 bitwidth

added a check script into ci

components/soc/esp32s2/include/soc/cp_dma_struct.h

@@ -69,6 +69,7 @@ typedef union {
          *  This is the interrupt raw bit. Triggered when crc calculation is done.
          */
         uint32_t dma_crc_done_int_raw: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_raw_reg_t;
@@ -123,6 +124,7 @@ typedef union {
          *  cp_crc_done_int_ena is set to 1.
          */
         uint32_t dma_crc_done_int_st: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_st_reg_t;
@@ -168,6 +170,7 @@ typedef union {
          *  This is the interrupt enable bit for cp_crc_done_int interrupt.
          */
         uint32_t dma_crc_done_int_ena: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_ena_reg_t;
@@ -213,6 +216,7 @@ typedef union {
          *  Set this bit to clear cp_crc_done_int interrupt.
          */
         uint32_t dma_crc_done_int_clr: 1;
+        uint32_t reserved9: 23;
     };
     uint32_t val;
 } cp_dma_int_clr_reg_t;
@@ -491,6 +495,7 @@ typedef union {
          *  Copy DMA FIFO empty signal.
          */
         uint32_t dma_fifo_empty: 1;
+        uint32_t reserved24: 8;
     };
     uint32_t val;
 } cp_dma_in_st_reg_t;
@@ -516,6 +521,7 @@ typedef union {
          *  Copy DMA FIFO full signal.
          */
         uint32_t dma_fifo_full: 1;
+        uint32_t reserved24: 8;
     };
     uint32_t val;
 } cp_dma_out_st_reg_t;