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Merge branch 'feat/ram_loadable_app_c5_c61' into 'master'

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ram_app: support c5 c61, fixed PMA15 occupied by ROM issue

Closes IDF-8644, IDF-9251, IDF-10315, and IDF-10951

See merge request espressif/esp-idf!33381
This commit is contained in:
Armando (Dou Yiwen)
2024-09-10 20:25:36 +08:00
parent 02c3445c66 9c81fe6114
commit 87b295a35f
13 changed files with 43 additions and 32 deletions
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6
components/bootloader_support/bootloader_flash/include/esp_private/bootloader_flash_internal.h
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@@ -28,12 +28,10 @@ esp_err_t bootloader_init_spi_flash(void);
void bootloader_flash_hardware_init(void);
#endif
#if SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
/**
* @brief Initialise flash core clock
* @brief Initialise mspi core clock
*/
void bootloader_flash_init_core_clock(void);
#endif //SOC_MEMSPI_FLASH_PSRAM_INDEPENDENT
void bootloader_init_mspi_clock(void);
#ifdef __cplusplus
}

16
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c5.c
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@@ -48,8 +48,18 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
bootloader_init_mspi_clock();
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -204,11 +214,7 @@ static void bootloader_spi_flash_resume(void)
esp_err_t bootloader_init_spi_flash(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C5 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
bootloader_init_mspi_clock();
bootloader_init_flash_configure();
bootloader_spi_flash_resume();

19
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32c61.c
View File

@@ -46,8 +46,19 @@ void IRAM_ATTR bootloader_flash_cs_timing_config()
SET_PERI_REG_BITS(SPI_MEM_CTRL2_REG(0), SPI_MEM_CS_SETUP_TIME_V, 0, SPI_MEM_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
}
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
bootloader_init_mspi_clock();
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {
case ESP_IMAGE_SPI_SPEED_DIV_1:
@@ -198,13 +209,7 @@ static void bootloader_spi_flash_resume(void)
esp_err_t bootloader_init_spi_flash(void)
{
// Set source mspi pll clock as 80M in bootloader stage.
// SPLL clock on C61 is 480MHz , and mspi_pll needs 80MHz
// in this stage, set divider as 6
mspi_ll_clock_src_sel(MSPI_CLK_SRC_SPLL);
mspi_ll_fast_set_hs_divider(6);
bootloader_init_mspi_clock();
bootloader_init_flash_configure();
bootloader_spi_flash_resume();
bootloader_flash_unlock();

4
components/bootloader_support/bootloader_flash/src/bootloader_flash_config_esp32p4.c
View File

@@ -42,7 +42,7 @@ void IRAM_ATTR bootloader_flash_cs_timing_config(void)
SET_PERI_REG_BITS(SPI_MEM_C_CTRL2_REG, SPI_MEM_C_CS_SETUP_TIME_V, 0, SPI_MEM_C_CS_SETUP_TIME_S);
}
void IRAM_ATTR bootloader_flash_init_core_clock(void)
void IRAM_ATTR bootloader_init_mspi_clock(void)
{
_spimem_flash_ll_select_clk_source(0, FLASH_CLK_SRC_SPLL);
_spimem_ctrlr_ll_set_core_clock(0, 6);
@@ -50,7 +50,7 @@ void IRAM_ATTR bootloader_flash_init_core_clock(void)
void IRAM_ATTR bootloader_flash_clock_config(const esp_image_header_t *pfhdr)
{
bootloader_flash_init_core_clock();
bootloader_init_mspi_clock();
uint32_t spi_clk_div = 0;
switch (pfhdr->spi_speed) {

2
components/bootloader_support/src/esp32p4/bootloader_esp32p4.c
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@@ -112,7 +112,7 @@ static inline void bootloader_hardware_init(void)
#if !CONFIG_APP_BUILD_TYPE_PURE_RAM_APP
// IDF-10019 TODO: This is temporarily for ESP32P4-ECO0, please remove it when eco0 is not widly used.
if (likely(ESP_CHIP_REV_ABOVE(chip_version, 1))) {
bootloader_flash_init_core_clock();
bootloader_init_mspi_clock();
}
#endif
}

1
components/esp_driver_sdspi/test_apps/sdspi/sdkconfig.defaults.esp32c5
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@@ -1 +1,2 @@
CONFIG_SDMMC_BOARD_ESP32C5_BREAKOUT=y
CONFIG_ESP_CONSOLE_USB_SERIAL_JTAG=y

2
components/esp_hw_support/port/esp32c5/cpu_region_protect.c
View File

@@ -69,6 +69,8 @@ static void esp_cpu_configure_invalid_regions(void)
// 8. End of address space
PMA_ENTRY_SET_TOR(14, SOC_PERIPHERAL_HIGH, PMA_NONE);
PMA_ENTRY_CFG_RESET(15);
PMA_ENTRY_SET_TOR(15, UINT32_MAX, PMA_TOR | PMA_NONE);
}

6
components/riscv/include/riscv/csr.h
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@@ -136,6 +136,12 @@ extern "C" {
RV_CLEAR_CSR((CSR_PMPCFG0) + (ENTRY)/4, (0xFF) << (ENTRY%4)*8); \
} while(0)
/*Reset all permissions of a particular PMACFG entry*/
#define PMA_ENTRY_CFG_RESET(ENTRY) do {\
RV_WRITE_CSR((CSR_PMACFG0) + (ENTRY) , 0); \
RV_WRITE_CSR((CSR_PMAADDR0) + (ENTRY) , 0); \
} while(0)
/********************************************************
Trigger Module register fields (Debug specification)
********************************************************/