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Merge branch 'feat/pwr_glitch_bringup_c5_c61' into 'master'

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feat(pwr_glitch): Add power glitch reset support on esp32c5, esp32c61

See merge request espressif/esp-idf!33032
This commit is contained in:
Jiang Jiang Jian
2024-10-15 14:15:49 +08:00
parent 2c71890bf8 858d0647e8
commit 88317cff24
11 changed files with 123 additions and 51 deletions
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63
components/soc/esp32c61/include/soc/regi2c_saradc.h
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@@ -18,41 +18,39 @@
#define I2C_SAR_ADC 0X69
#define I2C_SAR_ADC_HOSTID 0
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR 0x0
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR1_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR 0x1
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR1_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define ADC_SAR1_DREF_ADDR 0x2
#define ADC_SAR1_DREF_ADDR_MSB 0x6
#define ADC_SAR1_DREF_ADDR_LSB 0x4
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR 0x3
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_MSB 0x7
#define ADC_SAR2_INITIAL_CODE_LOW_ADDR_LSB 0x0
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR 0x4
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_MSB 0x3
#define ADC_SAR2_INITIAL_CODE_HIGH_ADDR_LSB 0x0
#define ADC_SAR2_DREF_ADDR 0x5
#define ADC_SAR2_DREF_ADDR_MSB 0x6
#define ADC_SAR2_DREF_ADDR_LSB 0x4
#define ADC_SAR1_SAMPLE_CYCLE_ADDR 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_MSB 0x2
#define ADC_SAR1_SAMPLE_CYCLE_ADDR_LSB 0x0
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
#define ADC_SARADC_DTEST_RTC_ADDR 0x7
#define ADC_SARADC_DTEST_RTC_ADDR_MSB 1
@@ -70,10 +68,31 @@
#define ADC_SARADC1_ENCAL_REF_ADDR_MSB 4
#define ADC_SARADC1_ENCAL_REF_ADDR_LSB 4
#define ADC_SAR1_ENCAL_GND_ADDR 0x7
#define ADC_SAR1_ENCAL_GND_ADDR_MSB 5
#define ADC_SAR1_ENCAL_GND_ADDR_LSB 5
#define ADC_SARADC2_ENCAL_REF_ADDR 0x7
#define ADC_SARADC2_ENCAL_REF_ADDR_MSB 6
#define ADC_SARADC2_ENCAL_REF_ADDR_LSB 6
#define I2C_SARADC_TSENS_DAC 0x6
#define I2C_SARADC_TSENS_DAC_MSB 3
#define I2C_SARADC_TSENS_DAC_LSB 0
#define ADC_SAR2_ENCAL_GND_ADDR 0x7
#define ADC_SAR2_ENCAL_GND_ADDR_MSB 7
#define ADC_SAR2_ENCAL_GND_ADDR_LSB 7
#define POWER_GLITCH_DREF_VDET_PERIF 11
#define POWER_GLITCH_DREF_VDET_PERIF_MSB 2
#define POWER_GLITCH_DREF_VDET_PERIF_LSB 0
#define POWER_GLITCH_DREF_VDET_VDDPST 11
#define POWER_GLITCH_DREF_VDET_VDDPST_MSB 6
#define POWER_GLITCH_DREF_VDET_VDDPST_LSB 4
#define POWER_GLITCH_DREF_VDET_PLLBB 12
#define POWER_GLITCH_DREF_VDET_PLLBB_MSB 2
#define POWER_GLITCH_DREF_VDET_PLLBB_LSB 0
#define POWER_GLITCH_DREF_VDET_PLL 12
#define POWER_GLITCH_DREF_VDET_PLL_MSB 6
#define POWER_GLITCH_DREF_VDET_PLL_LSB 4

5
components/soc/esp32c61/register/soc/lp_analog_peri_reg.h
View File

@@ -108,6 +108,11 @@ extern "C" {
#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
#define LP_ANA_ANA_FIB_ENA_S 0
#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA 0x0000000FU
#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_M (LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V << LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S)
#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_V 0x0000000FU
#define LP_ANA_ANA_FIB_PWR_GLITCH_ENA_S 2
/** LP_ANA_INT_RAW_REG register
* need_des
*/