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feat(i3c): i3c-i2c driver hal and soc support

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C.S.M
2025-02-10 15:40:57 +08:00
parent 9342b3fba1
commit 883c42b1f8
15 changed files with 905 additions and 1179 deletions
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16
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -343,6 +343,10 @@ config SOC_SIMD_INSTRUCTION_SUPPORTED
bool
default y
config SOC_I3C_MASTER_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_40M
bool
default y
@@ -2135,6 +2139,18 @@ config SOC_LCDCAM_CAM_DATA_WIDTH_MAX
int
default 16
config SOC_I3C_MASTER_PERIPH_NUM
bool
default y
config SOC_I3C_MASTER_ADDRESS_TABLE_NUM
int
default 12
config SOC_I3C_MASTER_COMMAND_TABLE_NUM
int
default 12
config SOC_LP_CORE_SUPPORT_ETM
bool
default y

15
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2023-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -736,6 +736,19 @@ typedef enum {
TEMPERATURE_SENSOR_CLK_SRC_DEFAULT = SOC_MOD_CLK_LP_PERI, /*!< Select LP_PERI as the default choice */
} soc_periph_temperature_sensor_clk_src_t;
//////////////////////////////////////////////////I3C Master///////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of I3C master
*/
#define SOC_I3C_MASTER_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M}
typedef enum {
I3C_MASTER_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL,
I3C_MASTER_CLK_SRC_PLL_F160M = SOC_MOD_CLK_PLL_F160M,
I3C_MASTER_CLK_SRC_DEFAULT = SOC_MOD_CLK_XTAL,
} soc_periph_i3c_master_clk_src_t;
//////////////////////////////////////////////////EMAC PTP///////////////////////////////////////////////////////////////
/**

8
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2022-2024 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -102,6 +102,7 @@
#define SOC_PM_SUPPORTED 1
#define SOC_BITSCRAMBLER_SUPPORTED 1
#define SOC_SIMD_INSTRUCTION_SUPPORTED 1
#define SOC_I3C_MASTER_SUPPORTED 1
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1
@@ -794,6 +795,11 @@
#define SOC_LCDCAM_CAM_PERIPH_NUM (1U)
#define SOC_LCDCAM_CAM_DATA_WIDTH_MAX (16U)
/*--------------------------- I3C ---------------------------------*/
#define SOC_I3C_MASTER_PERIPH_NUM (1)
#define SOC_I3C_MASTER_ADDRESS_TABLE_NUM (12)
#define SOC_I3C_MASTER_COMMAND_TABLE_NUM (12)
/*------------------------------------- ULP CAPS -------------------------------------*/
#define SOC_LP_CORE_SUPPORT_ETM (1) /*!< LP Core supports ETM */
#define SOC_LP_CORE_SUPPORT_LP_ADC (1) /*!< LP ADC can be accessed from the LP-Core */