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mcpwm: update hal and soc naming

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This commit is contained in:
morris
2021-07-06 00:12:25 +08:00
committed by suda-morris
parent 47c4e5d63e
commit 88c87bfe56
12 changed files with 388 additions and 277 deletions
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26
components/soc/esp32/include/soc/gpio_sig_map.h
View File

@@ -236,26 +236,8 @@
#define PWM1_CAP1_IN_IDX 113
#define PWM1_OUT2B_IDX 113
#define PWM1_CAP2_IN_IDX 114
#define PWM2_OUT1H_IDX 114
#define PWM2_FLTA_IDX 115
#define PWM2_OUT1L_IDX 115
#define PWM2_FLTB_IDX 116
#define PWM2_OUT2H_IDX 116
#define PWM2_CAP1_IN_IDX 117
#define PWM2_OUT2L_IDX 117
#define PWM2_CAP2_IN_IDX 118
#define PWM2_OUT3H_IDX 118
#define PWM2_CAP3_IN_IDX 119
#define PWM2_OUT3L_IDX 119
#define PWM3_FLTA_IDX 120
#define PWM2_OUT4H_IDX 120
#define PWM3_FLTB_IDX 121
#define PWM2_OUT4L_IDX 121
#define PWM3_CAP1_IN_IDX 122
#define PWM3_CAP2_IN_IDX 123
#define TWAI_TX_IDX 123
#define CAN_TX_IDX TWAI_TX_IDX
#define PWM3_CAP3_IN_IDX 124
#define TWAI_BUS_OFF_ON_IDX 124
#define CAN_BUS_OFF_ON_IDX TWAI_BUS_OFF_ON_IDX
#define TWAI_CLKOUT_IDX 125
@@ -369,19 +351,11 @@
#define I2S1O_DATA_OUT22_IDX 188
#define I2S1O_DATA_OUT23_IDX 189
#define I2S0I_H_SYNC_IDX 190
#define PWM3_OUT1H_IDX 190
#define I2S0I_V_SYNC_IDX 191
#define PWM3_OUT1L_IDX 191
#define I2S0I_H_ENABLE_IDX 192
#define PWM3_OUT2H_IDX 192
#define I2S1I_H_SYNC_IDX 193
#define PWM3_OUT2L_IDX 193
#define I2S1I_V_SYNC_IDX 194
#define PWM3_OUT3H_IDX 194
#define I2S1I_H_ENABLE_IDX 195
#define PWM3_OUT3L_IDX 195
#define PWM3_OUT4H_IDX 196
#define PWM3_OUT4L_IDX 197
#define U2RXD_IN_IDX 198
#define U2TXD_OUT_IDX 198
#define U2CTS_IN_IDX 199

5
components/soc/esp32/include/soc/soc_caps.h
View File

@@ -158,10 +158,11 @@
#define SOC_MCPWM_OPERATORS_PER_GROUP (3) ///< The number of operators that each group has
#define SOC_MCPWM_COMPARATORS_PER_OPERATOR (2) ///< The number of comparators that each operator has
#define SOC_MCPWM_GENERATORS_PER_OPERATOR (2) ///< The number of generators that each operator has
#define SOC_MCPWM_FAULT_DETECTORS_PER_GROUP (3) ///< The number of fault signal detectors that each group has
#define SOC_MCPWM_TRIGGERS_PER_OPERATOR (2) ///< The number of triggers that each operator has
#define SOC_MCPWM_GPIO_FAULTS_PER_GROUP (3) ///< The number of GPIO fault signals that each group has
#define SOC_MCPWM_CAPTURE_TIMERS_PER_GROUP (1) ///< The number of capture timers that each group has
#define SOC_MCPWM_CAPTURE_CHANNELS_PER_TIMER (3) ///< The number of capture channels that each capture timer has
#define SOC_MCPWM_EXT_SYNCERS_PER_GROUP (3) ///< The number of external syncers that each group has
#define SOC_MCPWM_GPIO_SYNCHROS_PER_GROUP (3) ///< The number of GPIO synchros that each group has
#define SOC_MCPWM_BASE_CLK_HZ (160000000ULL) ///< Base Clock frequency of 160MHz
/*-------------------------- MPU CAPS ----------------------------------------*/

8
components/soc/esp32/mcpwm_periph.c
View File

@@ -53,7 +53,7 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
}
}
},
.detectors = {
.gpio_faults = {
[0] = {
.fault_sig = PWM0_F0_IN_IDX
},
@@ -75,7 +75,7 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
.cap_sig = PWM0_CAP2_IN_IDX
}
},
.ext_syncers = {
.gpio_synchros = {
[0] = {
.sync_sig = PWM0_SYNC0_IN_IDX
},
@@ -122,7 +122,7 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
}
}
},
.detectors = {
.gpio_faults = {
[0] = {
.fault_sig = PWM1_F0_IN_IDX
},
@@ -144,7 +144,7 @@ const mcpwm_signal_conn_t mcpwm_periph_signals = {
.cap_sig = PWM1_CAP2_IN_IDX
}
},
.ext_syncers = {
.gpio_synchros = {
[0] = {
.sync_sig = PWM1_SYNC0_IN_IDX
},