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Merge branch 'bugfix/lp_uart_baudrate_limitation_v5.2' into 'release/v5.2'

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fix(uart): LP UART does not have the pre-divider for its clock source (v5.2)

See merge request espressif/esp-idf!37596
This commit is contained in:
morris
2025-03-17 11:06:13 +08:00
parent 7d12731212 ce808b09cd
commit 899b08a033
20 changed files with 212 additions and 219 deletions
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60
components/hal/esp32p4/include/hal/uart_ll.h
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@@ -17,6 +17,7 @@
#include "soc/uart_reg.h"
#include "soc/uart_struct.h"
#include "soc/hp_sys_clkrst_struct.h"
#include "soc/hp_sys_clkrst_reg.h"
#include "soc/lp_uart_reg.h"
#include "soc/lp_clkrst_struct.h"
#include "soc/lpperi_struct.h"
@@ -141,24 +142,25 @@ static inline void lp_uart_ll_set_source_clk(uart_dev_t *hw, soc_periph_lp_uart_
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool lp_uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->clk_conf, sclk_div_num, sclk_div - 1);
#undef DIV_UP
if (baud == 0) {
return false;
}
// No pre-divider for LP UART clock source on the target
uint32_t clk_div = (sclk_freq << 4) / baud;
// The baud rate configuration register is divided into an integer part and a fractional part.
uint32_t clkdiv_int = clk_div >> 4;
if (clkdiv_int > UART_CLKDIV_V) {
return false; // unachievable baud-rate
}
uint32_t clkdiv_frag = clk_div & 0xf;
hw->clkdiv_sync.clkdiv = clkdiv_int;
hw->clkdiv_sync.clkdiv_frag = clkdiv_frag;
uart_ll_update(hw);
return true;
}
/**
@@ -467,18 +469,28 @@ FORCE_INLINE_ATTR void uart_ll_get_sclk(uart_dev_t *hw, soc_module_clk_t *source
* @param baud The baud rate to be set.
* @param sclk_freq Frequency of the clock source of UART, in Hz.
*
* @return None
* @return True if baud-rate set successfully; False if baud-rate requested cannot be achieved
*/
FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
FORCE_INLINE_ATTR bool uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint32_t sclk_freq)
{
if ((hw) == &LP_UART) {
abort(); // need to call lp_uart_ll_set_baudrate()
}
#define DIV_UP(a, b) (((a) + (b) - 1) / (b))
const uint32_t max_div = BIT(12) - 1; // UART divider integer part only has 12 bits
if (baud == 0) {
return false;
}
const uint32_t max_div = UART_CLKDIV_V; // UART divider integer part only has 12 bits
uint32_t sclk_div = DIV_UP(sclk_freq, (uint64_t)max_div * baud);
if (sclk_div == 0) abort();
#undef DIV_UP
if (sclk_div == 0 || sclk_div > (HP_SYS_CLKRST_REG_UART0_SCLK_DIV_NUM_V + 1)) {
return false; // unachievable baud-rate
}
uint32_t clk_div = ((sclk_freq) << 4) / (baud * sclk_div);
// The baud rate configuration register is divided into
// an integer part and a fractional part.
// The baud rate configuration register is divided into an integer part and a fractional part.
hw->clkdiv_sync.clkdiv = clk_div >> 4;
hw->clkdiv_sync.clkdiv_frag = clk_div & 0xf;
//needs force u32 write
@@ -495,12 +507,12 @@ FORCE_INLINE_ATTR void uart_ll_set_baudrate(uart_dev_t *hw, uint32_t baud, uint3
} else {
abort();
}
#undef DIV_UP
uart_ll_update(hw);
return true;
}
#if !BOOTLOADER_BUILD
//HP_SYS_CLKRST.peri_clk_ctrlxxx are shared registers, so this function must be used in an atomic way
#define uart_ll_set_baudrate(...) (void)__DECLARE_RCC_ATOMIC_ENV; uart_ll_set_baudrate(__VA_ARGS__)
#define uart_ll_set_baudrate(...) uart_ll_set_baudrate(__VA_ARGS__); (void)__DECLARE_RCC_ATOMIC_ENV
#endif
/**
@@ -527,7 +539,7 @@ FORCE_INLINE_ATTR uint32_t uart_ll_get_baudrate(uart_dev_t *hw, uint32_t sclk_fr
} else if ((hw) == &UART4) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(HP_SYS_CLKRST.peri_clk_ctrl115, reg_uart4_sclk_div_num) + 1;
} else if ((hw) == &LP_UART) {
sclk_div = HAL_FORCE_READ_U32_REG_FIELD(hw->clk_conf, sclk_div_num) + 1;
sclk_div = 1; // no pre-divider for LP UART clock source on the target
}
return ((sclk_freq << 4)) / (((div_reg.clkdiv << 4) | div_reg.clkdiv_frag) * sclk_div);
}