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Merge branch 'bugfix/i2c_master_stretch_to' into 'master'

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fix(i2c_master): Fix an I2C issue that slave streth happen but master timeout seems not work

Closes IDFGH-13191 and IDFGH-13508

See merge request espressif/esp-idf!33014
This commit is contained in:
C.S.M
2024-08-29 17:29:30 +08:00
parent 796d40a6a7 8aee667873
commit 89c808c26c
9 changed files with 62 additions and 51 deletions
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13
components/hal/esp32c2/include/hal/i2c_ll.h
View File

@@ -583,7 +583,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@@ -647,7 +647,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@@ -675,7 +675,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
@@ -756,7 +756,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@@ -791,7 +792,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@@ -906,7 +907,7 @@ static inline void i2c_ll_master_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.

15
components/hal/esp32c3/include/hal/i2c_ll.h
View File

@@ -663,7 +663,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@@ -698,7 +698,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
@@ -770,7 +770,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@@ -798,7 +798,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
@@ -929,7 +929,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@@ -968,7 +969,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@@ -1155,7 +1156,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.

3
components/hal/esp32c5/include/hal/i2c_ll.h
View File

@@ -967,7 +967,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////

5
components/hal/esp32c6/include/hal/i2c_ll.h
View File

@@ -734,7 +734,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@@ -972,7 +972,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////

3
components/hal/esp32c61/include/hal/i2c_ll.h
View File

@@ -893,7 +893,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////

15
components/hal/esp32h2/include/hal/i2c_ll.h
View File

@@ -613,7 +613,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@@ -648,7 +648,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
@@ -720,7 +720,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@@ -748,7 +748,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
@@ -879,7 +879,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@@ -918,7 +919,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@@ -1106,7 +1107,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.

15
components/hal/esp32p4/include/hal/i2c_ll.h
View File

@@ -615,7 +615,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@@ -650,7 +650,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
@@ -722,7 +722,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@@ -750,7 +750,7 @@ static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
hw->scl_sp_conf.scl_rst_slv_en = 1;
hw->ctr.conf_upgate = 1;
// hardward will clear scl_rst_slv_en after sending SCL pulses,
// hardware will clear scl_rst_slv_en after sending SCL pulses,
// and we should set conf_upgate bit to synchronize register value.
while (hw->scl_sp_conf.scl_rst_slv_en);
hw->ctr.conf_upgate = 1;
@@ -976,7 +976,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@@ -1015,7 +1016,7 @@ typedef enum {
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@@ -1203,7 +1204,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param hight_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.

13
components/hal/esp32s3/include/hal/i2c_ll.h
View File

@@ -671,7 +671,7 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
*
* @param hw Beginning address of the peripheral registers
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*
* @return None.
*/
@@ -706,7 +706,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be writen
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
@@ -778,7 +778,7 @@ static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
}
/**
* @brief Reste I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
* @brief reset I2C master FSM. When the master FSM is stuck, call this function to reset the FSM
*
* @param hw Beginning address of the peripheral registers
*
@@ -931,7 +931,8 @@ static inline bool i2c_ll_master_is_cmd_done(i2c_dev_t *hw, int cmd_idx)
static inline uint32_t i2c_ll_calculate_timeout_us_to_reg_val(uint32_t src_clk_hz, uint32_t timeout_us)
{
uint32_t clk_cycle_num_per_us = src_clk_hz / (1 * 1000 * 1000);
return 31 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
// round up to an integer
return 32 - __builtin_clz(clk_cycle_num_per_us * timeout_us);
}
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
@@ -986,7 +987,7 @@ static inline void i2c_ll_get_scl_clk_timing(i2c_dev_t *hw, int *high_period, in
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
* @param wait_high_period The I2C SCL wait rising edge period.
*
@@ -1157,7 +1158,7 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
* @brief Configure I2C SCL timing
*
* @param hw Beginning address of the peripheral registers
* @param high_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
* @param high_period The I2C SCL height period (in core clock cycle, hight_period > 2)
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
*
* @return None.