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test(uhci): enable the psram test in CI

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This commit is contained in:
morris
2025-04-30 10:40:29 +08:00
parent 852466ea0e
commit 8af9bb624e
10 changed files with 27 additions and 12 deletions
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1
components/esp_driver_uart/test_apps/.build-test-rules.yml
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@@ -32,6 +32,5 @@ components/esp_driver_uart/test_apps/uart_vfs:
components/esp_driver_uart/test_apps/uhci:
disable:
- if: SOC_UHCI_SUPPORTED != 1
- if: CONFIG_NAME == "psram" and SOC_AHB_GDMA_SUPPORT_PSRAM != 1
depends_components:
- esp_driver_uart

4
components/esp_driver_uart/test_apps/uhci/main/test_uhci.c
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@@ -121,7 +121,7 @@ static void uhci_receive_test(void *arg)
uhci_controller_handle_t uhci_ctrl = ((uhci_controller_handle_t *)arg)[0];
SemaphoreHandle_t exit_sema = ((SemaphoreHandle_t *)arg)[1];
uhci_context_t *ctx = calloc(1, sizeof(uhci_context_t));
uhci_context_t *ctx = heap_caps_calloc(1, sizeof(uhci_context_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
assert(ctx);
ctx->uhci_queue = xQueueCreate(15, sizeof(uhci_event_t));
assert(ctx->uhci_queue);
@@ -252,7 +252,7 @@ static void uhci_receive_test_in_psram(void *arg)
uhci_controller_handle_t uhci_ctrl = ((uhci_controller_handle_t *)arg)[0];
SemaphoreHandle_t exit_sema = ((SemaphoreHandle_t *)arg)[1];
uhci_context_t *ctx = calloc(1, sizeof(uhci_context_t));
uhci_context_t *ctx = heap_caps_calloc(1, sizeof(uhci_context_t), MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
assert(ctx);
ctx->uhci_queue = xQueueCreate(15, sizeof(uhci_event_t));
assert(ctx->uhci_queue);

17
components/esp_driver_uart/test_apps/uhci/pytest_uhci.py
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@@ -3,7 +3,6 @@
import pytest
from pytest_embedded import Dut
from pytest_embedded_idf.utils import idf_parametrize
from pytest_embedded_idf.utils import soc_filtered_targets
@pytest.mark.generic
@@ -15,6 +14,20 @@ from pytest_embedded_idf.utils import soc_filtered_targets
],
indirect=True,
)
@idf_parametrize('target', soc_filtered_targets('SOC_UHCI_SUPPORTED == 1'), indirect=['target'])
@idf_parametrize('target', ['esp32c3', 'esp32c5', 'esp32c6', 'esp32h2', 'esp32p4'], indirect=['target'])
def test_uhci(dut: Dut) -> None:
dut.run_all_single_board_cases()
@pytest.mark.octal_psram
@pytest.mark.parametrize(
'config',
[
'cache_safe',
'release',
],
indirect=True,
)
@idf_parametrize('target', ['esp32s3'], indirect=['target'])
def test_uhci_psram_s3(dut: Dut) -> None:
dut.run_all_single_board_cases()

1
components/esp_driver_uart/test_apps/uhci/sdkconfig.ci.cache_safe
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@@ -6,6 +6,5 @@ CONFIG_COMPILER_OPTIMIZATION_NONE=y
CONFIG_FREERTOS_PLACE_FUNCTIONS_INTO_FLASH=y
# silent the error check, as the error string are stored in rodata, causing RTL check failure
CONFIG_COMPILER_OPTIMIZATION_CHECKS_SILENT=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_SILENT=y
CONFIG_HAL_ASSERTION_SILENT=y
CONFIG_COMPILER_OPTIMIZATION_ASSERTIONS_DISABLE=y

1
components/esp_driver_uart/test_apps/uhci/sdkconfig.ci.psram
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@@ -1 +0,0 @@
CONFIG_SPIRAM=y

3
components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32c5 Normal file
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@@ -0,0 +1,3 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_SPEED_40M=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0

4
components/esp_driver_uart/test_apps/uhci/sdkconfig.defaults.esp32s3 Normal file
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@@ -0,0 +1,4 @@
CONFIG_SPIRAM=y
CONFIG_SPIRAM_MODE_OCT=y
CONFIG_SPIRAM_SPEED_80M=y
CONFIG_SPIRAM_MALLOC_ALWAYSINTERNAL=0