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fix(uart): LP UART does not have the pre-divider for its clock source

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Closes https://github.com/espressif/esp-idf/issues/15427
This commit is contained in:
Song Ruo Jing
2025-02-24 21:27:41 +08:00
parent 6f9979451b
commit 8baffe22cb
21 changed files with 289 additions and 318 deletions
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50
components/soc/esp32c6/include/soc/lp_uart_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -100,7 +100,7 @@ extern "C" {
#define LP_UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U
#define LP_UART_RXFIFO_TOUT_INT_RAW_S 8
/** LP_UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* This interrupt raw bit turns to high level when receiver receives Xon char when
* uart_sw_flow_con_en is set to 1.
*/
#define LP_UART_SW_XON_INT_RAW (BIT(9))
@@ -671,7 +671,7 @@ extern "C" {
#define LP_UART_STOP_BIT_NUM_V 0x00000003U
#define LP_UART_STOP_BIT_NUM_S 4
/** LP_UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
* Set this bit to enbale transmitter to send NULL when the process of sending data
* Set this bit to enable transmitter to send NULL when the process of sending data
* is done.
*/
#define LP_UART_TXD_BRK (BIT(6))
@@ -1151,7 +1151,7 @@ extern "C" {
*/
#define LP_UART_TOUT_CONF_SYNC_REG (DR_REG_LP_UART_BASE + 0x64)
/** LP_UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
* This is the enble bit for uart receiver's timeout function.
* This is the enable bit for uart receiver's timeout function.
*/
#define LP_UART_RX_TOUT_EN (BIT(0))
#define LP_UART_RX_TOUT_EN_M (LP_UART_RX_TOUT_EN_V << LP_UART_RX_TOUT_EN_S)
@@ -1235,48 +1235,6 @@ extern "C" {
* UART core clock configuration
*/
#define LP_UART_CLK_CONF_REG (DR_REG_LP_UART_BASE + 0x88)
/** LP_UART_SCLK_DIV_B : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_B 0x0000003FU
#define LP_UART_SCLK_DIV_B_M (LP_UART_SCLK_DIV_B_V << LP_UART_SCLK_DIV_B_S)
#define LP_UART_SCLK_DIV_B_V 0x0000003FU
#define LP_UART_SCLK_DIV_B_S 0
/** LP_UART_SCLK_DIV_A : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_A 0x0000003FU
#define LP_UART_SCLK_DIV_A_M (LP_UART_SCLK_DIV_A_V << LP_UART_SCLK_DIV_A_S)
#define LP_UART_SCLK_DIV_A_V 0x0000003FU
#define LP_UART_SCLK_DIV_A_S 6
/** LP_UART_SCLK_DIV_NUM : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
#define LP_UART_SCLK_DIV_NUM 0x000000FFU
#define LP_UART_SCLK_DIV_NUM_M (LP_UART_SCLK_DIV_NUM_V << LP_UART_SCLK_DIV_NUM_S)
#define LP_UART_SCLK_DIV_NUM_V 0x000000FFU
#define LP_UART_SCLK_DIV_NUM_S 12
/** LP_UART_SCLK_SEL : R/W; bitpos: [21:20]; default: 3;
* UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.
*/
#define LP_UART_SCLK_SEL 0x00000003U
#define LP_UART_SCLK_SEL_M (LP_UART_SCLK_SEL_V << LP_UART_SCLK_SEL_S)
#define LP_UART_SCLK_SEL_V 0x00000003U
#define LP_UART_SCLK_SEL_S 20
/** LP_UART_SCLK_EN : R/W; bitpos: [22]; default: 1;
* Set this bit to enable UART Tx/Rx clock.
*/
#define LP_UART_SCLK_EN (BIT(22))
#define LP_UART_SCLK_EN_M (LP_UART_SCLK_EN_V << LP_UART_SCLK_EN_S)
#define LP_UART_SCLK_EN_V 0x00000001U
#define LP_UART_SCLK_EN_S 22
/** LP_UART_RST_CORE : R/W; bitpos: [23]; default: 0;
* Write 1 then write 0 to this bit to reset UART Tx/Rx.
*/
#define LP_UART_RST_CORE (BIT(23))
#define LP_UART_RST_CORE_M (LP_UART_RST_CORE_V << LP_UART_RST_CORE_S)
#define LP_UART_RST_CORE_V 0x00000001U
#define LP_UART_RST_CORE_S 23
/** LP_UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/

35
components/soc/esp32c6/include/soc/lp_uart_struct.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -49,7 +49,7 @@ typedef union {
typedef union {
struct {
/** rx_tout_en : R/W; bitpos: [0]; default: 0;
* This is the enble bit for uart receiver's timeout function.
* This is the enable bit for uart receiver's timeout function.
*/
uint32_t rx_tout_en:1;
/** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
@@ -120,7 +120,7 @@ typedef union {
*/
uint32_t rxfifo_tout:1;
/** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* This interrupt raw bit turns to high level when receiver receives Xon char when
* uart_sw_flow_con_en is set to 1.
*/
uint32_t sw_xon:1;
@@ -466,7 +466,7 @@ typedef union {
*/
uint32_t stop_bit_num:2;
/** txd_brk : R/W; bitpos: [6]; default: 0;
* Set this bit to enbale transmitter to send NULL when the process of sending data
* Set this bit to enable transmitter to send NULL when the process of sending data
* is done.
*/
uint32_t txd_brk:1;
@@ -791,30 +791,7 @@ typedef union {
*/
typedef union {
struct {
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
uint32_t sclk_div_b:6;
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
uint32_t sclk_div_a:6;
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
uint32_t sclk_div_num:8;
/** sclk_sel : R/W; bitpos: [21:20]; default: 3;
* UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.
*/
uint32_t sclk_sel:2;
/** sclk_en : R/W; bitpos: [22]; default: 1;
* Set this bit to enable UART Tx/Rx clock.
*/
uint32_t sclk_en:1;
/** rst_core : R/W; bitpos: [23]; default: 0;
* Write 1 then write 0 to this bit to reset UART Tx/Rx.
*/
uint32_t rst_core:1;
uint32_t reserved_20:24;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/
@@ -1115,7 +1092,7 @@ typedef struct lp_uart_dev_t {
volatile lp_uart_id_reg_t id;
} lp_uart_dev_t;
// We map the LP_UART instance to the uart_dev_t struct for convinience of using the same HAL/LL. See soc/uart_struct.h
// We map the LP_UART instance to the uart_dev_t struct for convenience of using the same HAL/LL. See soc/uart_struct.h
// extern lp_uart_dev_t LP_UART;
#ifndef __cplusplus

44
components/soc/esp32c6/include/soc/uart_reg.h
View File

@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -100,7 +100,7 @@ extern "C" {
#define UART_RXFIFO_TOUT_INT_RAW_V 0x00000001U
#define UART_RXFIFO_TOUT_INT_RAW_S 8
/** UART_SW_XON_INT_RAW : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* This interrupt raw bit turns to high level when receiver receives Xon char when
* uart_sw_flow_con_en is set to 1.
*/
#define UART_SW_XON_INT_RAW (BIT(9))
@@ -760,7 +760,7 @@ extern "C" {
#define UART_STOP_BIT_NUM_V 0x00000003U
#define UART_STOP_BIT_NUM_S 4
/** UART_TXD_BRK : R/W; bitpos: [6]; default: 0;
* Set this bit to enbale transmitter to send NULL when the process of sending data
* Set this bit to enable transmitter to send NULL when the process of sending data
* is done.
*/
#define UART_TXD_BRK (BIT(6))
@@ -1326,7 +1326,7 @@ extern "C" {
*/
#define UART_TOUT_CONF_SYNC_REG(i) (REG_UART_BASE(i) + 0x64)
/** UART_RX_TOUT_EN : R/W; bitpos: [0]; default: 0;
* This is the enble bit for uart receiver's timeout function.
* This is the enable bit for uart receiver's timeout function.
*/
#define UART_RX_TOUT_EN (BIT(0))
#define UART_RX_TOUT_EN_M (UART_RX_TOUT_EN_V << UART_RX_TOUT_EN_S)
@@ -1450,7 +1450,7 @@ extern "C" {
*/
#define UART_HIGHPULSE_REG(i) (REG_UART_BASE(i) + 0x80)
/** UART_HIGHPULSE_MIN_CNT : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the maxinum duration time for the high level
* This register stores the value of the maximum duration time for the high level
* pulse. It is used in baud rate-detect process.
*/
#define UART_HIGHPULSE_MIN_CNT 0x00000FFFU
@@ -1471,6 +1471,40 @@ extern "C" {
#define UART_RXD_EDGE_CNT_V 0x000003FFU
#define UART_RXD_EDGE_CNT_S 0
/** UART_CLK_CONF_REG register
* UART core clock configuration
*/
#define UART_CLK_CONF_REG(i) (REG_UART_BASE(i) + 0x88)
/** UART_TX_SCLK_EN : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/
#define UART_TX_SCLK_EN (BIT(24))
#define UART_TX_SCLK_EN_M (UART_TX_SCLK_EN_V << UART_TX_SCLK_EN_S)
#define UART_TX_SCLK_EN_V 0x00000001U
#define UART_TX_SCLK_EN_S 24
/** UART_RX_SCLK_EN : R/W; bitpos: [25]; default: 1;
* Set this bit to enable UART Rx clock.
*/
#define UART_RX_SCLK_EN (BIT(25))
#define UART_RX_SCLK_EN_M (UART_RX_SCLK_EN_V << UART_RX_SCLK_EN_S)
#define UART_RX_SCLK_EN_V 0x00000001U
#define UART_RX_SCLK_EN_S 25
/** UART_TX_RST_CORE : R/W; bitpos: [26]; default: 0;
* Write 1 then write 0 to this bit to reset UART Tx.
*/
#define UART_TX_RST_CORE (BIT(26))
#define UART_TX_RST_CORE_M (UART_TX_RST_CORE_V << UART_TX_RST_CORE_S)
#define UART_TX_RST_CORE_V 0x00000001U
#define UART_TX_RST_CORE_S 26
/** UART_RX_RST_CORE : R/W; bitpos: [27]; default: 0;
* Write 1 then write 0 to this bit to reset UART Rx.
*/
#define UART_RX_RST_CORE (BIT(27))
#define UART_RX_RST_CORE_M (UART_RX_RST_CORE_V << UART_RX_RST_CORE_S)
#define UART_RX_RST_CORE_V 0x00000001U
#define UART_RX_RST_CORE_S 27
/** UART_DATE_REG register
* UART Version register
*/

37
components/soc/esp32c6/include/soc/uart_struct.h
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@@ -1,5 +1,5 @@
/**
* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2022-2025 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -49,7 +49,7 @@ typedef union {
typedef union {
struct {
/** rx_tout_en : R/W; bitpos: [0]; default: 0;
* This is the enble bit for uart receiver's timeout function.
* This is the enable bit for uart receiver's timeout function.
*/
uint32_t rx_tout_en:1;
/** rx_tout_flow_dis : R/W; bitpos: [1]; default: 0;
@@ -120,7 +120,7 @@ typedef union {
*/
uint32_t rxfifo_tout:1;
/** sw_xon : R/WTC/SS; bitpos: [9]; default: 0;
* This interrupt raw bit turns to high level when receiver recevies Xon char when
* This interrupt raw bit turns to high level when receiver receives Xon char when
* uart_sw_flow_con_en is set to 1.
*/
uint32_t sw_xon:1;
@@ -515,7 +515,7 @@ typedef union {
*/
uint32_t stop_bit_num:2;
/** txd_brk : R/W; bitpos: [6]; default: 0;
* Set this bit to enbale transmitter to send NULL when the process of sending data
* Set this bit to enable transmitter to send NULL when the process of sending data
* is done.
*/
uint32_t txd_brk:1;
@@ -880,30 +880,7 @@ typedef union {
*/
typedef union {
struct {
/** sclk_div_b : R/W; bitpos: [5:0]; default: 0;
* The denominator of the frequency divider factor.
*/
uint32_t sclk_div_b:6;
/** sclk_div_a : R/W; bitpos: [11:6]; default: 0;
* The numerator of the frequency divider factor.
*/
uint32_t sclk_div_a:6;
/** sclk_div_num : R/W; bitpos: [19:12]; default: 1;
* The integral part of the frequency divider factor.
*/
uint32_t sclk_div_num:8;
/** sclk_sel : R/W; bitpos: [21:20]; default: 3;
* UART clock source select. 1: 80Mhz. 2: 8Mhz. 3: XTAL.
*/
uint32_t sclk_sel:2;
/** sclk_en : R/W; bitpos: [22]; default: 1;
* Set this bit to enable UART Tx/Rx clock.
*/
uint32_t sclk_en:1;
/** rst_core : R/W; bitpos: [23]; default: 0;
* Write 1 then write 0 to this bit to reset UART Tx/Rx.
*/
uint32_t rst_core:1;
uint32_t reserved_0:24;
/** tx_sclk_en : R/W; bitpos: [24]; default: 1;
* Set this bit to enable UART Tx clock.
*/
@@ -1170,7 +1147,7 @@ typedef union {
typedef union {
struct {
/** highpulse_min_cnt : RO; bitpos: [11:0]; default: 4095;
* This register stores the value of the maxinum duration time for the high level
* This register stores the value of the maximum duration time for the high level
* pulse. It is used in baud rate-detect process.
*/
uint32_t highpulse_min_cnt:12;
@@ -1273,7 +1250,7 @@ typedef struct uart_dev_s {
volatile uart_lowpulse_reg_t lowpulse; /* LP_UART instance has this register reserved */
volatile uart_highpulse_reg_t highpulse; /* LP_UART instance has this register reserved */
volatile uart_rxd_cnt_reg_t rxd_cnt; /* LP_UART instance has this register reserved */
volatile uart_clk_conf_reg_t clk_conf; /* UART0/1 instance have this register reserved, configure in corresponding PCR registers */
volatile uart_clk_conf_reg_t clk_conf;
volatile uart_date_reg_t date;
volatile uart_afifo_status_reg_t afifo_status;
uint32_t reserved_094;