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esp32: make time monotonic across resets
Small changes to clock calibration value will cause increasing errors
the longer the device runs. Consider the case of deep sleep, assuming
that RTC counter is used for timekeeping:
- before sleep:
time_before = rtc_counter * calibration_val
- after sleep:
time_after = (rtc_counter + sleep_count) * (calibration_val + epsilon)
where 'epsilon' is a small estimation error of 'calibration_val'.
The apparent sleep duration thus will be:
time_after - time_before = sleep_count * (calibration_val + epsilon)
+ rtc_counter * epsilon
Second term on the right hand side is the error in time difference
estimation, it is proportional to the total system runtime (rtc_counter).
To avoid this issue, this change makes RTC_SLOW_CLK calibration value
persistent across restarts. This allows the calibration value update to
be preformed, while keeping time after update same as before the update.
This commit is contained in:
@@ -33,7 +33,7 @@ void esp_clk_init(void);
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/**
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* @brief Get the cached calibration value of RTC slow clock
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* @brief Get the calibration value of RTC slow clock
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*
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* The value is in the same format as returned by rtc_clk_cal (microseconds,
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* in Q13.19 fixed-point format).
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@@ -42,3 +42,15 @@ void esp_clk_init(void);
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*/
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uint32_t esp_clk_slowclk_cal_get();
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/**
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* @brief Update the calibration value of RTC slow clock
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*
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* The value has to be in the same format as returned by rtc_clk_cal (microseconds,
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* in Q13.19 fixed-point format).
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* This value is used by timekeeping functions (such as gettimeofday) to
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* calculate current time based on RTC counter value.
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* @param value calibration value obtained using rtc_clk_cal
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*/
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void esp_clk_slowclk_cal_set(uint32_t value);
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@@ -50,9 +50,9 @@ extern "C" {
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* 0x3ff80000(0x400c0000) Fast 8192 deep sleep entry code
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*
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*************************************************************************************
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* Rtc store registers usage
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* RTC_CNTL_STORE0_REG
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* RTC_CNTL_STORE1_REG
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* RTC store registers usage
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* RTC_CNTL_STORE0_REG Reserved
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* RTC_CNTL_STORE1_REG RTC_SLOW_CLK calibration value
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* RTC_CNTL_STORE2_REG Boot time, low word
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* RTC_CNTL_STORE3_REG Boot time, high word
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* RTC_CNTL_STORE4_REG External XTAL frequency
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@@ -62,6 +62,7 @@ extern "C" {
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*************************************************************************************
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*/
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#define RTC_SLOW_CLK_CAL_REG RTC_CNTL_STORE1_REG
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#define RTC_BOOT_TIME_LOW_REG RTC_CNTL_STORE2_REG
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#define RTC_BOOT_TIME_HIGH_REG RTC_CNTL_STORE3_REG
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#define RTC_XTAL_FREQ_REG RTC_CNTL_STORE4_REG
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