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Merge branch 'refactor/i2c_ll_trm_sync' into 'master'

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refactor(i2c): rename some LL functions according to TRM descriptions

See merge request espressif/esp-idf!35049
This commit is contained in:
morris
2024-11-22 10:13:29 +08:00
parent 36d5d8c31c 3fb7461eb0
commit 8da529e5eb
17 changed files with 162 additions and 144 deletions
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29
components/hal/esp32c6/include/hal/i2c_ll.h
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@@ -303,7 +303,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
*
* @return None
*/
static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
static inline void i2c_ll_enable_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
{
hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
}
@@ -322,7 +322,7 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
}
/**
* @brief Configure I2C slave broadcasting mode.
* @brief Enable the I2C slave to respond to broadcast address
*
* @param hw Beginning address of the peripheral registers
* @param broadcast_en Set true to enable broadcast, else, set it false
@@ -456,6 +456,7 @@ static inline void i2c_ll_set_sda_timing(i2c_dev_t *hw, int sda_sample, int sda_
*/
static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->fifo_conf.txfifo_wm_thrhd = empty_thr;
}
@@ -470,6 +471,7 @@ static inline void i2c_ll_set_txfifo_empty_thr(i2c_dev_t *hw, uint8_t empty_thr)
static inline void i2c_ll_set_rxfifo_full_thr(i2c_dev_t *hw, uint8_t full_thr)
{
hw->fifo_conf.fifo_prt_en = 1;
hw->ctr.rx_full_ack_level = 0;
hw->fifo_conf.rxfifo_wm_thrhd = full_thr;
}
@@ -586,7 +588,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
* @return None
*/
__attribute__((always_inline))
static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
static inline void i2c_ll_start_trans(i2c_dev_t *hw)
{
hw->ctr.trans_start = 1;
}
@@ -634,7 +636,7 @@ __attribute__((always_inline))
static inline void i2c_ll_write_txfifo(i2c_dev_t *hw, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
HAL_FORCE_MODIFY_U32_REG_FIELD(hw->data, fifo_rdata, ptr[i]);
hw->data.val = ptr[i];
}
}
@@ -656,14 +658,14 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
}
/**
* @brief Write the I2C hardware txFIFO
* @brief Write to the TX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs to be written
*/
static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
static inline void i2c_ll_write_tx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
hw->txfifo_mem[i + ram_offset] = ptr[i];
@@ -671,14 +673,14 @@ static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, co
}
/**
* @brief Read the I2C hardware ram
* @brief Read from the RX RAM by direct address
*
* @param hw Beginning address of the peripheral registers
* @param ram_offset Offset value of I2C RAM.
* @param ptr Pointer to data buffer
* @param len Amount of data needs read
*/
static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
static inline void i2c_ll_read_rx_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
{
for (int i = 0; i < len; i++) {
ptr[i] = hw->rxfifo_mem[i + ram_offset];
@@ -686,14 +688,16 @@ static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uin
}
/**
* @brief Get access to I2C RAM address directly
* @brief Enable I2C slave dual addressing mode
*
* @note When enable the dual addressing mode, I2C RAM must be accessed in non-FIFO mode
*
* @param hw Beginning address of the peripheral registers
* @param addr_wr_en Enable I2C ram address read and write
*
* @return None
*/
static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
static inline void i2c_ll_slave_enable_dual_addressing_mode(i2c_dev_t *hw, bool addr_wr_en)
{
hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
}
@@ -914,16 +918,15 @@ static inline void i2c_ll_slave_init(i2c_dev_t *hw)
ctrl_reg.sda_force_out = 0;
ctrl_reg.scl_force_out = 0;
hw->ctr.val = ctrl_reg.val;
hw->fifo_conf.fifo_addr_cfg_en = 0;
}
/**
* @brief Set whether slave should auto start, or only start with start signal from master
* @brief Enable I2C slave to automatically send data when addressed by the master
*
* @param hw Beginning address of the peripheral registers
* @param slv_ex_auto_en 1 if slave auto start data transaction, otherwise, 0.
*/
static inline void i2c_ll_slave_tx_auto_start_en(i2c_dev_t *hw, bool slv_ex_auto_en)
static inline void i2c_ll_slave_enable_auto_start(i2c_dev_t *hw, bool slv_ex_auto_en)
{
hw->ctr.slv_tx_auto_start_en = slv_ex_auto_en;
}