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feat(esp32c5mp): support to build g0 components

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This commit is contained in:
laokaiyao
2024-03-13 19:32:32 +08:00
parent 0d8dcd183c
commit 8de41350eb
12 changed files with 31 additions and 6 deletions
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4
components/soc/esp32c5/beta3/include/soc/Kconfig.soc_caps.in
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@@ -75,6 +75,10 @@ config SOC_SPI_FLASH_SUPPORTED
bool
default y
config SOC_MODEM_CLOCK_SUPPORTED
bool
default y
config SOC_XTAL_SUPPORT_40M
bool
default y

1
components/soc/esp32c5/beta3/include/soc/soc_caps.h
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@@ -74,6 +74,7 @@
// #define SOC_HUK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8617
// #define SOC_LIGHT_SLEEP_SUPPORTED 1 // TODO: [ESP32C5] IDF-8640
// #define SOC_DEEP_SLEEP_SUPPORTED 1 // TODO: [ESP32C5] IDF-8638
#define SOC_MODEM_CLOCK_SUPPORTED 1 // TODO: [ESP32C5] IDF-8845 need check, it is opened because pll has been used on beta3
/*-------------------------- XTAL CAPS ---------------------------------------*/
#define SOC_XTAL_SUPPORT_40M 1