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fix(spi): Correct REG_SPI_BASE(i) macro for all targets

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The existing formula can never match these registers.

Closes https://github.com/espressif/esp-idf/pull/12559
Closes https://github.com/espressif/esp-idf/pull/12562
This commit is contained in:
TD-er
2023-11-10 22:43:04 +01:00
committed by wanlei
parent 5cf65ce766
commit 8e0d64e94c
15 changed files with 42 additions and 73 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
components/soc/esp32c2/include/soc/soc.h
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@@ -30,6 +30,7 @@
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{ //Registers Operation {{

3
components/soc/esp32c2/include/soc/spi_reg.h
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@@ -6,12 +6,11 @@
#ifndef _SOC_SPI_REG_H_ #ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_
#include "soc/soc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "soc/soc.h"
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */

1
components/soc/esp32c2/ld/esp32c2.peripherals.ld
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@@ -16,7 +16,6 @@ PROVIDE ( LEDC = 0x60019000 );
PROVIDE ( TIMERG0 = 0x6001F000 ); PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI2 = 0x60024000 );
PROVIDE ( GPSPI3 = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( GDMA = 0x6003F000 );

1
components/soc/esp32c3/include/soc/soc.h
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@@ -23,6 +23,7 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Registers Operation {{ //Registers Operation {{

20
components/soc/esp32c3/include/soc/spi_reg.h
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@@ -1,24 +1,16 @@
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_REG_H_ #ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_
#include "soc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "soc.h"
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x0)
/* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */ /* SPI_USR : R/W/SC ;bitpos:[24] ;default: 1'b0 ; */

2
components/soc/esp32c3/ld/esp32c3.peripherals.ld
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@@ -26,10 +26,8 @@ PROVIDE ( TIMERG0 = 0x6001F000 );
PROVIDE ( TIMERG1 = 0x60020000 ); PROVIDE ( TIMERG1 = 0x60020000 );
PROVIDE ( SYSTIMER = 0x60023000 ); PROVIDE ( SYSTIMER = 0x60023000 );
PROVIDE ( GPSPI2 = 0x60024000 ); PROVIDE ( GPSPI2 = 0x60024000 );
PROVIDE ( GPSPI3 = 0x60025000 );
PROVIDE ( SYSCON = 0x60026000 ); PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( TWAI = 0x6002B000 ); PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( APB_SARADC = 0x60040000 ); PROVIDE ( APB_SARADC = 0x60040000 );
PROVIDE ( USB_SERIAL_JTAG = 0x60043000 ); PROVIDE ( USB_SERIAL_JTAG = 0x60043000 );
PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( GDMA = 0x6003F000 );

4
components/soc/esp32c6/include/soc/soc.h
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@@ -23,10 +23,10 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6 #define REG_I2S_BASE(i) (DR_REG_I2S_BASE) // only one I2S on C6
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1 #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i) * 0x1000) // TIMERG0 and TIMERG1
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1 #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) // SPIMEM0 and SPIMEM1
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE) // only one GPSPI on C6 #define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI on C6
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6 #define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE) // only one I2C on C6
#define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6 #define REG_MCPWM_BASE(i) (DR_REG_MCPWM_BASE) // only one MCPWM on C6
#define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1 #define REG_TWAI_BASE(i) (DR_REG_TWAI0_BASE + (i) * 0x2000) // TWAI0 and TWAI1
//Registers Operation {{ //Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_UNCACHED_ADDR(addr) (addr)

2
components/soc/esp32h2/include/soc/soc.h
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@@ -23,8 +23,8 @@
#define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_I2S_BASE(i) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE + (i) * 0x1000)
#define REG_SPI_BASE(i) (((i)==2) ? (DR_REG_SPI2_BASE) : (0)) // only one GPSPI
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000) #define REG_I2C_BASE(i) (DR_REG_I2C_EXT0_BASE + (i) * 0x1000)
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (i - 2) * 0x1000)
//Registers Operation {{ //Registers Operation {{
#define ETS_UNCACHED_ADDR(addr) (addr) #define ETS_UNCACHED_ADDR(addr) (addr)

1
components/soc/esp32s2/include/soc/reg_base.h
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@@ -56,7 +56,6 @@
#define DR_REG_SYSCON_BASE 0x3f426000 #define DR_REG_SYSCON_BASE 0x3f426000
#define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */ #define DR_REG_APB_CTRL_BASE 0x3f426000 /* Old name for SYSCON, to be removed */
#define DR_REG_I2C1_EXT_BASE 0x3f427000 #define DR_REG_I2C1_EXT_BASE 0x3f427000
#define DR_REG_SPI4_BASE 0x3f437000
#define DR_REG_USB_WRAP_BASE 0x3f439000 #define DR_REG_USB_WRAP_BASE 0x3f439000
#define DR_REG_APB_SARADC_BASE 0x3f440000 #define DR_REG_APB_SARADC_BASE 0x3f440000
#define DR_REG_USB_BASE 0x60080000 #define DR_REG_USB_BASE 0x60080000

17
components/soc/esp32s2/include/soc/soc.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -18,14 +18,15 @@
#define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space #define SOC_MAX_CONTIGUOUS_RAM_SIZE (SOC_EXTRAM_DATA_HIGH - SOC_EXTRAM_DATA_LOW) ///< Largest span of contiguous memory (DRAM or IRAM) in the address space
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE) #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 ) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE) #define REG_I2S_BASE( i ) (DR_REG_I2S_BASE)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Convenient way to replace the register ops when ulp riscv projects //Convenient way to replace the register ops when ulp riscv projects
//consume this file //consume this file

21
components/soc/esp32s2/include/soc/spi_mem_reg.h
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@@ -1,25 +1,16 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_MEM_REG_H_ #ifndef _SOC_SPI_MEM_REG_H_
#define _SOC_SPI_MEM_REG_H_ #define _SOC_SPI_MEM_REG_H_
#include "soc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "soc.h"
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000) #define SPI_MEM_CMD_REG(i) (REG_SPI_MEM_BASE(i) + 0x000)
/* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */ /* SPI_MEM_FLASH_READ : R/W ;bitpos:[31] ;default: 1'b0 ; */

21
components/soc/esp32s2/include/soc/spi_reg.h
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@@ -1,25 +1,16 @@
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD /*
// * SPDX-FileCopyrightText: 2017-2023 Espressif Systems (Shanghai) CO LTD
// Licensed under the Apache License, Version 2.0 (the "License"); *
// you may not use this file except in compliance with the License. * SPDX-License-Identifier: Apache-2.0
// You may obtain a copy of the License at */
//
// http://www.apache.org/licenses/LICENSE-2.0
//
// Unless required by applicable law or agreed to in writing, software
// distributed under the License is distributed on an "AS IS" BASIS,
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
// See the License for the specific language governing permissions and
// limitations under the License.
#ifndef _SOC_SPI_REG_H_ #ifndef _SOC_SPI_REG_H_
#define _SOC_SPI_REG_H_ #define _SOC_SPI_REG_H_
#include "soc.h"
#ifdef __cplusplus #ifdef __cplusplus
extern "C" { extern "C" {
#endif #endif
#include "soc.h"
#define REG_SPI_BASE(i) (DR_REG_SPI2_BASE + (((i)>3) ? (((i-2)* 0x1000) + 0x10000) : ((i - 2)* 0x1000 )))
#define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000) #define SPI_CMD_REG(i) (REG_SPI_BASE(i) + 0x000)
/* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */ /* SPI_USR : R/W ;bitpos:[24] ;default: 1'b0 ; */

17
components/soc/esp32s3/include/soc/soc.h
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@@ -1,5 +1,5 @@
/* /*
* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD * SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
* *
* SPDX-License-Identifier: Apache-2.0 * SPDX-License-Identifier: Apache-2.0
*/ */
@@ -27,14 +27,15 @@
#define DR_REG_EXT_MEM_ENC 0x600CC000 #define DR_REG_EXT_MEM_ENC 0x600CC000
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000) #define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)
#define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_BASE( i ) (DR_REG_UART_BASE + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) ) #define REG_UART_AHB_BASE(i) (0x60000000 + (i) * 0x10000 + ( (i) > 1 ? 0xe000 : 0 ) )
#define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0) #define UART_FIFO_AHB_REG(i) (REG_UART_AHB_BASE(i) + 0x0)
#define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000) #define REG_I2S_BASE( i ) (DR_REG_I2S_BASE + (i) * 0x1E000)
#define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000) #define REG_TIMG_BASE(i) (DR_REG_TIMERGROUP0_BASE + (i)*0x1000)
#define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000) #define REG_SPI_MEM_BASE(i) (DR_REG_SPI0_BASE - (i) * 0x1000)
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 ) #define REG_SPI_BASE(i) (((i)>=2) ? (DR_REG_SPI2_BASE + (i-2) * 0x1000) : (0)) // GPSPI2 and GPSPI3
#define REG_I2C_BASE(i) (DR_REG_I2C_EXT_BASE + (i) * 0x14000 )
//Convenient way to replace the register ops when ulp riscv projects //Convenient way to replace the register ops when ulp riscv projects
//consume this file //consume this file

1
components/soc/esp32s3/ld/esp32s3.peripherals.ld
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@@ -38,7 +38,6 @@ PROVIDE ( SYSCON = 0x60026000 );
PROVIDE ( I2C1 = 0x60027000 ); PROVIDE ( I2C1 = 0x60027000 );
PROVIDE ( SDMMC = 0x60028000 ); PROVIDE ( SDMMC = 0x60028000 );
PROVIDE ( TWAI = 0x6002B000 ); PROVIDE ( TWAI = 0x6002B000 );
PROVIDE ( GPSPI4 = 0x60037000 );
PROVIDE ( GDMA = 0x6003F000 ); PROVIDE ( GDMA = 0x6003F000 );
PROVIDE ( UART2 = 0x6002E000 ); PROVIDE ( UART2 = 0x6002E000 );
PROVIDE ( DMA = 0x6003F000 ); PROVIDE ( DMA = 0x6003F000 );

3
tools/ci/check_copyright_ignore.txt
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@@ -835,7 +835,6 @@ components/soc/esp32c3/include/soc/sensitive_struct.h
components/soc/esp32c3/include/soc/soc_pins.h components/soc/esp32c3/include/soc/soc_pins.h
components/soc/esp32c3/include/soc/spi_mem_reg.h components/soc/esp32c3/include/soc/spi_mem_reg.h
components/soc/esp32c3/include/soc/spi_pins.h components/soc/esp32c3/include/soc/spi_pins.h
components/soc/esp32c3/include/soc/spi_reg.h
components/soc/esp32c3/include/soc/system_reg.h components/soc/esp32c3/include/soc/system_reg.h
components/soc/esp32c3/include/soc/system_struct.h components/soc/esp32c3/include/soc/system_struct.h
components/soc/esp32c3/include/soc/systimer_reg.h components/soc/esp32c3/include/soc/systimer_reg.h
@@ -878,9 +877,7 @@ components/soc/esp32s2/include/soc/sdmmc_pins.h
components/soc/esp32s2/include/soc/sens_reg.h components/soc/esp32s2/include/soc/sens_reg.h
components/soc/esp32s2/include/soc/sensitive_reg.h components/soc/esp32s2/include/soc/sensitive_reg.h
components/soc/esp32s2/include/soc/soc_ulp.h components/soc/esp32s2/include/soc/soc_ulp.h
components/soc/esp32s2/include/soc/spi_mem_reg.h
components/soc/esp32s2/include/soc/spi_pins.h components/soc/esp32s2/include/soc/spi_pins.h
components/soc/esp32s2/include/soc/spi_reg.h
components/soc/esp32s2/include/soc/systimer_reg.h components/soc/esp32s2/include/soc/systimer_reg.h
components/soc/esp32s2/include/soc/systimer_struct.h components/soc/esp32s2/include/soc/systimer_struct.h
components/soc/esp32s2/include/soc/touch_sensor_channel.h components/soc/esp32s2/include/soc/touch_sensor_channel.h