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mspi: refactor timing tuning driver to make it compatible with p4

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This commit is contained in:
Armando
2023-04-04 15:49:45 +08:00
parent 39e93a95a3
commit 8eec6558d1
21 changed files with 1331 additions and 924 deletions
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31
components/hal/esp32s3/include/hal/mspi_timing_tuning_ll.h
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@@ -35,6 +35,8 @@ extern "C" {
#define MSPI_TIMING_LL_FLASH_FAST_MODE_MASK (SPI_MEM_FASTRD_MODE)
#define MSPI_TIMING_LL_FLASH_SLOW_MODE_MASK 0
#define MSPI_TIMING_LL_CORE_CLOCK_MHZ_DEFAULT 80
typedef enum {
MSPI_TIMING_LL_FLASH_OPI_MODE = BIT(0),
MSPI_TIMING_LL_FLASH_QIO_MODE = BIT(1),
@@ -133,15 +135,34 @@ static inline void mspi_timing_ll_enable_flash_variable_dummy(uint8_t spi_num, b
}
/**
* Set MSPI core clock divider
* Set MSPI core clock
*
* @param spi_num SPI0 / SPI1
* @param val Divider value
* @param spi_num SPI0 / SPI1
* @param core_clk_mhz core clock mhz
*/
__attribute__((always_inline))
static inline void mspi_timing_ll_set_core_clock_divider(uint8_t spi_num, uint32_t val)
static inline void mspi_timing_ll_set_core_clock(uint8_t spi_num, uint32_t core_clk_mhz)
{
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, val);
uint32_t reg_val = 0;
switch (core_clk_mhz) {
case 80:
reg_val = 0;
break;
case 120:
reg_val = 1;
break;
case 160:
reg_val = 2;
break;
case 240:
reg_val = 3;
break;
default:
HAL_ASSERT(false);
}
REG_SET_FIELD(SPI_MEM_CORE_CLK_SEL_REG(spi_num), SPI_MEM_CORE_CLK_SEL, reg_val);
}
/**