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dac: optimize the dma stratege

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This commit is contained in:
laokaiyao
2022-10-10 19:17:22 +08:00
parent f9f9a09dfb
commit 8ef9fd4623
113 changed files with 9163 additions and 7830 deletions
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21
components/hal/esp32s2/include/hal/dac_ll.h
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@@ -68,6 +68,7 @@ static inline void dac_ll_power_down(dac_channel_t channel)
* @param value Output value. Value range: 0 ~ 255.
* The corresponding range of voltage is 0v ~ VDD3P3_RTC.
*/
__attribute__((always_inline))
static inline void dac_ll_update_output_value(dac_channel_t channel, uint8_t value)
{
if (channel == DAC_CHAN_0) {
@@ -125,7 +126,7 @@ static inline void dac_ll_cw_generator_disable(void)
* @param channel DAC channel num.
* @param enable
*/
static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
static inline void dac_ll_cw_enable_channel(dac_channel_t channel, bool enable)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_cw_en1 = enable;
@@ -138,12 +139,12 @@ static inline void dac_ll_cw_set_channel(dac_channel_t channel, bool enable)
* Set frequency of cosine wave generator output.
*
* @note We know that CLK8M is about 8M, but don't know the actual value. so this freq have limited error.
* @param freq_hz CW generator frequency. Range: >= 130(130Hz)
* @param freq_hz CW generator frequency. Range: >= 130Hz, no exact ceiling limitation, but will distort when reach several MHz
* @param rtc8m_freq the calibrated RTC 8M clock frequency
*/
static inline void dac_ll_cw_set_freq(uint32_t freq, uint32_t rtc8m_freq)
{
uint32_t sw_freq = (uint32_t)(((float)freq / (float)rtc8m_freq) * 65536);
uint32_t sw_freq = (uint32_t)(((uint64_t)freq << 16) / rtc8m_freq);
HAL_FORCE_MODIFY_U32_REG_FIELD(SENS.sar_dac_ctrl1, sw_fstep, (sw_freq > 0xFFFF) ? 0xFFFF : sw_freq);
}
@@ -151,14 +152,18 @@ static inline void dac_ll_cw_set_freq(uint32_t freq, uint32_t rtc8m_freq)
* Set the amplitude of the cosine wave generator output.
*
* @param channel DAC channel num.
* @param scale The multiple of the amplitude. The max amplitude is VDD3P3_RTC.
* @param atten The attenuation of the amplitude. The max amplitude is VDD3P3_RTC.
* 0: attenuation = 1, amplitude = VDD3P3_RTC / attenuation,
* 1: attenuation = 2, amplitude = VDD3P3_RTC / attenuation,
* 2: attenuation = 4, amplitude = VDD3P3_RTC / attenuation,
* 3: attenuation = 8, amplitude = VDD3P3_RTC / attenuation
*/
static inline void dac_ll_cw_set_scale(dac_channel_t channel, uint32_t scale)
static inline void dac_ll_cw_set_atten(dac_channel_t channel, dac_cosine_atten_t atten)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_scale1 = scale;
SENS.sar_dac_ctrl2.dac_scale1 = atten;
} else if (channel == DAC_CHAN_1) {
SENS.sar_dac_ctrl2.dac_scale2 = scale;
SENS.sar_dac_ctrl2.dac_scale2 = atten;
}
}
@@ -168,7 +173,7 @@ static inline void dac_ll_cw_set_scale(dac_channel_t channel, uint32_t scale)
* @param channel DAC channel num.
* @param phase Phase value. 0: 0x02 180: 0x03.
*/
static inline void dac_ll_cw_set_phase(dac_channel_t channel, uint32_t phase)
static inline void dac_ll_cw_set_phase(dac_channel_t channel, dac_cosine_phase_t phase)
{
if (channel == DAC_CHAN_0) {
SENS.sar_dac_ctrl2.dac_inv1 = phase;

1
components/hal/esp32s2/include/hal/spi_ll.h
View File

@@ -1260,6 +1260,7 @@ static inline void spi_dma_ll_enable_out_auto_wrback(spi_dma_dev_t *dma_out, uin
* @param channel DMA channel, for chip version compatibility, not used.
* @return The address
*/
__attribute__((always_inline))
static inline uint32_t spi_dma_ll_get_out_eof_desc_addr(spi_dma_dev_t *dma_out, uint32_t channel)
{
return dma_out->dma_out_eof_des_addr;