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fix(gpio): add workaround to ensure correct IO drive strength for C3 and S3

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This commit is contained in:
Song Ruo Jing
2024-03-22 18:06:29 +08:00
parent 573bd1bcc9
commit 90a3107bfd
3 changed files with 39 additions and 9 deletions
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16
components/hal/esp32s3/include/hal/rtc_io_ll.h
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@@ -1,5 +1,5 @@
/*
* SPDX-FileCopyrightText: 2015-2023 Espressif Systems (Shanghai) CO LTD
* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
@@ -155,7 +155,12 @@ static inline uint32_t rtcio_ll_get_level(int rtcio_num)
static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strength)
{
if (rtc_io_desc[rtcio_num].drv_v) {
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, strength, rtc_io_desc[rtcio_num].drv_s);
uint32_t drv_cap = strength;
// DRV = 1 and DRV = 2 register bits are flipped for IO17, IO18 on the target
if (rtcio_num == RTCIO_GPIO17_CHANNEL || rtcio_num == RTCIO_GPIO18_CHANNEL) {
drv_cap = ((drv_cap & 0x1) << 1) | ((drv_cap & 0x2) >> 1); // swap bit0 and bit1
}
SET_PERI_REG_BITS(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, drv_cap, rtc_io_desc[rtcio_num].drv_s);
}
}
@@ -167,7 +172,12 @@ static inline void rtcio_ll_set_drive_capability(int rtcio_num, uint32_t strengt
*/
static inline uint32_t rtcio_ll_get_drive_capability(int rtcio_num)
{
return GET_PERI_REG_BITS2(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, rtc_io_desc[rtcio_num].drv_s);
uint32_t strength = GET_PERI_REG_BITS2(rtc_io_desc[rtcio_num].reg, rtc_io_desc[rtcio_num].drv_v, rtc_io_desc[rtcio_num].drv_s);
// DRV = 1 and DRV = 2 register bits are flipped for IO17, IO18 on the target
if (rtcio_num == RTCIO_GPIO17_CHANNEL || rtcio_num == RTCIO_GPIO18_CHANNEL) {
strength = ((strength & 0x1) << 1) | ((strength & 0x2) >> 1); // swap bit0 and bit1
}
return strength;
}
/**