feat(etm): add core driver support for esp32-p4

esp_etm core driver support:
- channel allocator
- gpio etm sub driver
- gptimer etm sub driver

components/esp_hw_support/esp_etm.c

@@ -28,6 +28,13 @@
 
 #define ETM_MEM_ALLOC_CAPS   MALLOC_CAP_DEFAULT
 
+#if CONFIG_IDF_TARGET_ESP32P4
+// Reset and Clock Control registers are mixing with other peripherals, so we need to use a critical section
+#define ETM_RCC_ATOMIC() PERIPH_RCC_ATOMIC()
+#else
+#define ETM_RCC_ATOMIC()
+#endif
+
 static const char *TAG = "etm";
 
 typedef struct etm_platform_t etm_platform_t;
@@ -78,10 +85,12 @@ static etm_group_t *etm_acquire_group_handle(int group_id)
             // initialize ETM group members
             group->group_id = group_id;
             group->spinlock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
-            // enable APB access ETM registers
+            // enable bus clock for the ETM registers
-            // if we have multiple ETM groups/instances, we assume the peripheral defines are continuous
+            ETM_RCC_ATOMIC() {
-            periph_module_enable(PERIPH_ETM_MODULE + group_id);
+                etm_ll_enable_bus_clock(group_id, true);
-            periph_module_reset(PERIPH_ETM_MODULE + group_id);
+                etm_ll_reset_register(group_id);
+            }
+
             // initialize HAL context
             etm_hal_init(&group->hal);
         }
@@ -112,7 +121,10 @@ static void etm_release_group_handle(etm_group_t *group)
         assert(s_platform.groups[group_id]);
         do_deinitialize = true;
         s_platform.groups[group_id] = NULL; // deregister from platform
-        periph_module_disable(PERIPH_ETM_MODULE + group_id);
+        // disable the bus clock for the ETM registers
+        ETM_RCC_ATOMIC() {
+            etm_ll_enable_bus_clock(group_id, false);
+        }
     }
     _lock_release(&s_platform.mutex);
 

components/esp_hw_support/test_apps/etm/main/test_gptimer_etm.c

@@ -342,7 +342,7 @@ TEST_CASE("gptimer_etm_task_capture", "[etm]")
     TEST_ESP_OK(gptimer_enable(gptimer));
     TEST_ESP_OK(gptimer_start(gptimer));
 
-    vTaskDelay(pdMS_TO_TICKS(500));
+    esp_rom_delay_us(500 * 1000);
 
     // simulate the edge signal by software
     TEST_ESP_OK(gpio_set_level(input_gpio, 1));
@@ -432,7 +432,7 @@ TEST_CASE("gptimer_start_stop_by_etm_task", "[etm]")
 
     // trigger an pos-edge, this should start the gptimer
     TEST_ESP_OK(gpio_set_level(input_gpio, 1));
-    vTaskDelay(pdMS_TO_TICKS(500));
+    esp_rom_delay_us(500 * 1000);
     uint64_t cur_count_val = 0;
     TEST_ESP_OK(gptimer_get_raw_count(gptimer, &cur_count_val));
     printf("cur_count_val: %llu\r\n", cur_count_val);
@@ -442,7 +442,7 @@ TEST_CASE("gptimer_start_stop_by_etm_task", "[etm]")
     TEST_ESP_OK(gpio_set_level(input_gpio, 0));
     uint64_t count_val_0 = 0;
     TEST_ESP_OK(gptimer_get_raw_count(gptimer, &count_val_0));
-    vTaskDelay(pdMS_TO_TICKS(500));
+    esp_rom_delay_us(500 * 1000);
     uint64_t count_val_1 = 0;
     TEST_ESP_OK(gptimer_get_raw_count(gptimer, &count_val_1));
     TEST_ASSERT_EQUAL(count_val_0, count_val_1);

components/hal/esp32c6/include/hal/etm_ll.h

@@ -1,5 +1,5 @@
 /*
- * SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
+ * SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -12,20 +12,34 @@
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "soc/soc_etm_struct.h"
+#include "soc/pcr_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
- * @brief Enable the clock for ETM module
+ * @brief Enable the clock for ETM register
  *
- * @param hw ETM register base address
+ * @param group_id Group ID
  * @param enable true to enable, false to disable
  */
-static inline void etm_ll_enable_clock(soc_etm_dev_t *hw, bool enable)
+static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
 {
-    hw->clk_en.clk_en = enable;
+    (void)group_id;
+    PCR.etm_conf.etm_clk_en = enable;
+}
+
+/**
+ * @brief Reset the ETM register
+ *
+ * @param group_id Group ID
+ */
+static inline void etm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.etm_conf.etm_rst_en = 1;
+    PCR.etm_conf.etm_rst_en = 0;
 }
 
 /**

components/hal/esp32h2/include/hal/etm_ll.h

@@ -12,20 +12,34 @@
 #include "hal/assert.h"
 #include "hal/misc.h"
 #include "soc/soc_etm_struct.h"
+#include "soc/pcr_struct.h"
 
 #ifdef __cplusplus
 extern "C" {
 #endif
 
 /**
- * @brief Enable the clock for ETM module
+ * @brief Enable the clock for ETM register
  *
- * @param hw ETM register base address
+ * @param group_id Group ID
  * @param enable true to enable, false to disable
  */
-static inline void etm_ll_enable_clock(soc_etm_dev_t *hw, bool enable)
+static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
 {
-    hw->clk_en.clk_en = enable;
+    (void)group_id;
+    PCR.etm_conf.etm_clk_en = enable;
+}
+
+/**
+ * @brief Reset the ETM register
+ *
+ * @param group_id Group ID
+ */
+static inline void etm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    PCR.etm_conf.etm_rst_en = 1;
+    PCR.etm_conf.etm_rst_en = 0;
 }
 
 /**

components/hal/esp32p4/include/hal/etm_ll.h

@@ -0,0 +1,126 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "soc/soc_etm_struct.h"
+#include "soc/hp_sys_clkrst_struct.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable the bus clock for ETM module
+ *
+ * @param group_id Group ID
+ * @param enable true to enable, false to disable
+ */
+static inline void etm_ll_enable_bus_clock(int group_id, bool enable)
+{
+    (void)group_id;
+    HP_SYS_CLKRST.soc_clk_ctrl3.reg_etm_apb_clk_en = enable;
+    HP_SYS_CLKRST.soc_clk_ctrl1.reg_etm_sys_clk_en = enable;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define etm_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_enable_bus_clock(__VA_ARGS__)
+
+/**
+ * @brief Reset the ETM module
+ *
+ * @param group_id Group ID
+ */
+static inline void etm_ll_reset_register(int group_id)
+{
+    (void)group_id;
+    HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_etm = 1;
+    HP_SYS_CLKRST.hp_rst_en1.reg_rst_en_etm = 0;
+}
+
+/// use a macro to wrap the function, force the caller to use it in a critical section
+/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
+#define etm_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; etm_ll_reset_register(__VA_ARGS__)
+
+/**
+ * @brief Enable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_enable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_set.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_set.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Disable ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ */
+static inline void etm_ll_disable_channel(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        hw->ch_ena_ad0_clr.val = 1 << chan;
+    } else {
+        hw->ch_ena_ad1_clr.val = 1 << (chan - 32);
+    }
+}
+
+/**
+ * @brief Check whether the ETM channel is enabled or not
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @return true if the channel is enabled, false otherwise
+ */
+static inline bool etm_ll_is_channel_enabled(soc_etm_dev_t *hw, uint32_t chan)
+{
+    if (chan < 32) {
+        return hw->ch_ena_ad0.val & (1 << chan);
+    } else {
+        return hw->ch_ena_ad1.val & (1 << (chan - 32));
+    }
+}
+
+/**
+ * @brief Set the input event for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param event Event ID
+ */
+static inline void etm_ll_channel_set_event(soc_etm_dev_t *hw, uint32_t chan, uint32_t event)
+{
+    hw->channel[chan].evt_id.evt_id = event;
+}
+
+/**
+ * @brief Set the output task for the ETM channel
+ *
+ * @param hw ETM register base address
+ * @param chan Channel ID
+ * @param task Task ID
+ */
+static inline void etm_ll_channel_set_task(soc_etm_dev_t *hw, uint32_t chan, uint32_t task)
+{
+    hw->channel[chan].task_id.task_id = task;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32p4/include/hal/gpio_etm_ll.h

@@ -0,0 +1,119 @@
+/*
+ * SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+// Note that most of the register operations in this layer are non-atomic operations.
+
+#pragma once
+
+#include <stdbool.h>
+#include "hal/assert.h"
+#include "hal/misc.h"
+#include "soc/gpio_ext_struct.h"
+#include "soc/soc_etm_source.h"
+
+#define GPIO_LL_ETM_EVENT_ID_POS_EDGE(ch) (GPIO_EVT_CH0_RISE_EDGE + (ch))
+#define GPIO_LL_ETM_EVENT_ID_NEG_EDGE(ch) (GPIO_EVT_CH0_FALL_EDGE + (ch))
+#define GPIO_LL_ETM_EVENT_ID_ANY_EDGE(ch) (GPIO_EVT_CH0_ANY_EDGE + (ch))
+
+#define GPIO_LL_ETM_TASK_ID_SET(ch) (GPIO_TASK_CH0_SET + (ch))
+#define GPIO_LL_ETM_TASK_ID_CLR(ch) (GPIO_TASK_CH0_CLEAR + (ch))
+#define GPIO_LL_ETM_TASK_ID_TOG(ch) (GPIO_TASK_CH0_TOGGLE + (ch))
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set which GPIO to be bounded to the event channel
+ *
+ * @param dev Register base address
+ * @param chan Channel number
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_etm_event_channel_set_gpio(gpio_etm_dev_t *dev, uint32_t chan, uint32_t gpio_num)
+{
+    dev->etm_event_chn_cfg[chan].etm_chn_event_sel = gpio_num;
+}
+
+/**
+ * @brief Wether to enable the event channel
+ *
+ * @param dev Register base address
+ * @param chan Channel number
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_etm_enable_event_channel(gpio_etm_dev_t *dev, uint32_t chan, bool enable)
+{
+    dev->etm_event_chn_cfg[chan].etm_chn_event_en = enable;
+}
+
+/**
+ * @brief Set which GPIO to be bounded to the task channel
+ *
+ * @note One channel can be bounded to multiple different GPIOs
+ *
+ * @param dev Register base address
+ * @param chan Channel number
+ * @param gpio_num GPIO number
+ */
+static inline void gpio_ll_etm_gpio_set_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num, uint32_t chan)
+{
+    int g_p = gpio_num / 4;
+    int g_idx = gpio_num % 4;
+    uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
+    reg_val &= ~(0x07 << (g_idx * 8 + 1));
+    reg_val |= ((chan & 0x07) << (g_idx * 8 + 1));
+    dev->etm_task_pn_cfg[g_p].val = reg_val;
+}
+
+/**
+ * @brief Wether to enable the GPIO to be managed by the task channel
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @param enable True to enable, false to disable
+ */
+static inline void gpio_ll_etm_enable_task_gpio(gpio_etm_dev_t *dev, uint32_t gpio_num, bool enable)
+{
+    int g_p = gpio_num / 4;
+    int g_idx = gpio_num % 4;
+    uint32_t reg_val = dev->etm_task_pn_cfg[g_p].val;
+    reg_val &= ~(0x01 << (g_idx * 8));
+    reg_val |= ((enable & 0x01) << (g_idx * 8));
+    dev->etm_task_pn_cfg[g_p].val = reg_val;
+}
+
+/**
+ * @brief Check whether a GPIO has been enabled and managed by a task channel
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @return True if enabled, false otherwise
+ */
+static inline bool gpio_ll_etm_is_task_gpio_enabled(gpio_etm_dev_t *dev, uint32_t gpio_num)
+{
+    int g_p = gpio_num / 4;
+    int g_idx = gpio_num % 4;
+    return dev->etm_task_pn_cfg[g_p].val & (0x01 << (g_idx * 8));
+}
+
+/**
+ * @brief Get the channel number that the GPIO is bounded to
+ *
+ * @param dev Register base address
+ * @param gpio_num GPIO number
+ * @return GPIO ETM Task channel number
+ */
+static inline uint32_t gpio_ll_etm_gpio_get_task_channel(gpio_etm_dev_t *dev, uint32_t gpio_num)
+{
+    int g_p = gpio_num / 4;
+    int g_idx = gpio_num % 4;
+    return (dev->etm_task_pn_cfg[g_p].val >> (g_idx * 8 + 1)) & 0x07;
+}
+
+#ifdef __cplusplus
+}
+#endif

components/hal/esp32p4/include/hal/timer_ll.h

@@ -24,6 +24,62 @@ extern "C" {
 #define TIMER_LL_GET_HW(group_id) ((group_id == 0) ? (&TIMERG0) : (&TIMERG1))
 #define TIMER_LL_EVENT_ALARM(timer_id) (1 << (timer_id))
 
+#define TIMER_LL_ETM_TASK_TABLE(group, timer, task)                         \
+    (uint32_t[2][2][GPTIMER_ETM_TASK_MAX]){                                 \
+        {                                                                   \
+            {                                                               \
+                [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER0, \
+                [GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER0,   \
+                [GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER0,  \
+                [GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER0,     \
+                [GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER0,       \
+            },                                                              \
+            {                                                               \
+                [GPTIMER_ETM_TASK_START_COUNT] = TG0_TASK_CNT_START_TIMER1, \
+                [GPTIMER_ETM_TASK_STOP_COUNT] = TG0_TASK_CNT_STOP_TIMER1,   \
+                [GPTIMER_ETM_TASK_EN_ALARM] = TG0_TASK_ALARM_START_TIMER1,  \
+                [GPTIMER_ETM_TASK_RELOAD] = TG0_TASK_CNT_RELOAD_TIMER1,     \
+                [GPTIMER_ETM_TASK_CAPTURE] = TG0_TASK_CNT_CAP_TIMER1,       \
+            },                                                              \
+        },                                                                  \
+        {                                                                   \
+            {                                                               \
+                [GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER0, \
+                [GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER0,   \
+                [GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER0,  \
+                [GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER0,     \
+                [GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER0,       \
+            },                                                              \
+            {                                                               \
+                [GPTIMER_ETM_TASK_START_COUNT] = TG1_TASK_CNT_START_TIMER1, \
+                [GPTIMER_ETM_TASK_STOP_COUNT] = TG1_TASK_CNT_STOP_TIMER1,   \
+                [GPTIMER_ETM_TASK_EN_ALARM] = TG1_TASK_ALARM_START_TIMER1,  \
+                [GPTIMER_ETM_TASK_RELOAD] = TG1_TASK_CNT_RELOAD_TIMER1,     \
+                [GPTIMER_ETM_TASK_CAPTURE] = TG1_TASK_CNT_CAP_TIMER1,       \
+            },                                                              \
+        },                                                                  \
+    }[group][timer][task]
+
+#define TIMER_LL_ETM_EVENT_TABLE(group, timer, event)                     \
+    (uint32_t[2][2][GPTIMER_ETM_EVENT_MAX]){                              \
+        {                                                                 \
+            {                                                             \
+                [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER0, \
+            },                                                            \
+            {                                                             \
+                [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG0_EVT_CNT_CMP_TIMER1, \
+            },                                                            \
+        },                                                                \
+        {                                                                 \
+            {                                                             \
+                [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER0, \
+            },                                                            \
+            {                                                             \
+                [GPTIMER_ETM_EVENT_ALARM_MATCH] = TG1_EVT_CNT_CMP_TIMER1, \
+            },                                                            \
+        },                                                                \
+    }[group][timer][event]
+
 /**
  * @brief Enable the bus clock for timer group module
  *

components/soc/esp32p4/include/soc/Kconfig.soc_caps.in

@@ -31,6 +31,10 @@ config SOC_MCPWM_SUPPORTED
     bool
     default y
 
+config SOC_ETM_SUPPORTED
+    bool
+    default y
+
 config SOC_ASYNC_MEMCPY_SUPPORTED
     bool
     default y
@@ -271,6 +275,10 @@ config SOC_GPIO_SUPPORT_PIN_HYS_FILTER
     bool
     default y
 
+config SOC_GPIO_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_GPIO_ETM_EVENTS_PER_GROUP
     int
     default 8
@@ -827,6 +835,10 @@ config SOC_TIMER_GROUP_TOTAL_TIMERS
     int
     default 4
 
+config SOC_TIMER_SUPPORT_ETM
+    bool
+    default y
+
 config SOC_TWAI_CONTROLLER_NUM
     int
     default 2

components/soc/esp32p4/include/soc/gpio_ext_struct.h

@@ -19,12 +19,12 @@ typedef union {
         /** duty : R/W; bitpos: [7:0]; default: 0;
          *  This field is used to configure the duty cycle of sigma delta modulation output.
          */
-        uint32_t duty:8;
+        uint32_t duty: 8;
         /** prescale : R/W; bitpos: [15:8]; default: 255;
          *  This field is used to set a divider value to divide APB clock.
          */
-        uint32_t prescale:8;
+        uint32_t prescale: 8;
-        uint32_t reserved_16:16;
+        uint32_t reserved_16: 16;
     };
     uint32_t val;
 } gpio_sigmadelta_chn_reg_t;
@@ -34,20 +34,19 @@ typedef union {
  */
 typedef union {
     struct {
-        uint32_t reserved_0:30;
+        uint32_t reserved_0: 30;
         /** function_clk_en : R/W; bitpos: [30]; default: 0;
          *  Clock enable bit of sigma delta modulation.
          */
-        uint32_t function_clk_en:1;
+        uint32_t function_clk_en: 1;
         /** spi_swap : R/W; bitpos: [31]; default: 0;
          *  Reserved.
          */
-        uint32_t spi_swap:1;
+        uint32_t spi_swap: 1;
     };
     uint32_t val;
 } gpio_sigmadelta_misc_reg_t;
 
-
 /** Group: Glitch filter Configure Registers */
 /** Type of glitch_filter_chn register
  *  Glitch Filter Configure Register of Channeln
@@ -57,25 +56,24 @@ typedef union {
         /** filter_chn_en : R/W; bitpos: [0]; default: 0;
          *  Glitch Filter channel enable bit.
          */
-        uint32_t filter_chn_en:1;
+        uint32_t filter_chn_en: 1;
         /** filter_chn_input_io_num : R/W; bitpos: [6:1]; default: 0;
          *  Glitch Filter input io number.
          */
-        uint32_t filter_chn_input_io_num:6;
+        uint32_t filter_chn_input_io_num: 6;
         /** filter_chn_window_thres : R/W; bitpos: [12:7]; default: 0;
          *  Glitch Filter window threshold.
          */
-        uint32_t filter_chn_window_thres:6;
+        uint32_t filter_chn_window_thres: 6;
         /** filter_chn_window_width : R/W; bitpos: [18:13]; default: 0;
          *  Glitch Filter window width.
          */
-        uint32_t filter_chn_window_width:6;
+        uint32_t filter_chn_window_width: 6;
-        uint32_t reserved_19:13;
+        uint32_t reserved_19: 13;
     };
     uint32_t val;
 } gpio_glitch_filter_chn_reg_t;
 
-
 /** Group: Etm Configure Registers */
 /** Type of etm_event_chn_cfg register
  *  Etm Config register of Channeln
@@ -85,13 +83,13 @@ typedef union {
         /** etm_chn_event_sel : R/W; bitpos: [5:0]; default: 0;
          *  Etm event channel select gpio.
          */
-        uint32_t etm_chn_event_sel:6;
+        uint32_t etm_chn_event_sel: 6;
-        uint32_t reserved_6:1;
+        uint32_t reserved_6: 1;
         /** etm_chn_event_en : R/W; bitpos: [7]; default: 0;
          *  Etm event send enable bit.
          */
-        uint32_t etm_chn_event_en:1;
+        uint32_t etm_chn_event_en: 1;
-        uint32_t reserved_8:24;
+        uint32_t reserved_8: 24;
     };
     uint32_t val;
 } gpio_etm_event_chn_cfg_reg_t;
@@ -104,619 +102,42 @@ typedef union {
         /** etm_task_gpio0_en : R/W; bitpos: [0]; default: 0;
          *  Enable bit of GPIO response etm task.
          */
-        uint32_t etm_task_gpio0_en:1;
+        uint32_t etm_task_gpio0_en: 1;
         /** etm_task_gpio0_sel : R/W; bitpos: [3:1]; default: 0;
          *  GPIO choose a etm task channel.
          */
-        uint32_t etm_task_gpio0_sel:3;
+        uint32_t etm_task_gpio0_sel: 3;
-        uint32_t reserved_4:4;
+        uint32_t reserved_4: 4;
         /** etm_task_gpio1_en : R/W; bitpos: [8]; default: 0;
          *  Enable bit of GPIO response etm task.
          */
-        uint32_t etm_task_gpio1_en:1;
+        uint32_t etm_task_gpio1_en: 1;
         /** etm_task_gpio1_sel : R/W; bitpos: [11:9]; default: 0;
          *  GPIO choose a etm task channel.
          */
-        uint32_t etm_task_gpio1_sel:3;
+        uint32_t etm_task_gpio1_sel: 3;
-        uint32_t reserved_12:4;
+        uint32_t reserved_12: 4;
         /** etm_task_gpio2_en : R/W; bitpos: [16]; default: 0;
          *  Enable bit of GPIO response etm task.
          */
-        uint32_t etm_task_gpio2_en:1;
+        uint32_t etm_task_gpio2_en: 1;
         /** etm_task_gpio2_sel : R/W; bitpos: [19:17]; default: 0;
          *  GPIO choose a etm task channel.
          */
-        uint32_t etm_task_gpio2_sel:3;
+        uint32_t etm_task_gpio2_sel: 3;
-        uint32_t reserved_20:4;
+        uint32_t reserved_20: 4;
         /** etm_task_gpio3_en : R/W; bitpos: [24]; default: 0;
          *  Enable bit of GPIO response etm task.
          */
-        uint32_t etm_task_gpio3_en:1;
+        uint32_t etm_task_gpio3_en: 1;
         /** etm_task_gpio3_sel : R/W; bitpos: [27:25]; default: 0;
          *  GPIO choose a etm task channel.
          */
-        uint32_t etm_task_gpio3_sel:3;
+        uint32_t etm_task_gpio3_sel: 3;
-        uint32_t reserved_28:4;
+        uint32_t reserved_28: 4;
     };
     uint32_t val;
-} gpio_etm_task_p0_cfg_reg_t;
+} gpio_etm_task_pn_cfg_reg_t;
-
-/** Type of etm_task_p1_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio4_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio4_en:1;
-        /** etm_task_gpio4_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio4_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio5_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio5_en:1;
-        /** etm_task_gpio5_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio5_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio6_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio6_en:1;
-        /** etm_task_gpio6_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio6_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio7_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio7_en:1;
-        /** etm_task_gpio7_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio7_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p1_cfg_reg_t;
-
-/** Type of etm_task_p2_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio8_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio8_en:1;
-        /** etm_task_gpio8_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio8_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio9_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio9_en:1;
-        /** etm_task_gpio9_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio9_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio10_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio10_en:1;
-        /** etm_task_gpio10_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio10_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio11_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio11_en:1;
-        /** etm_task_gpio11_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio11_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p2_cfg_reg_t;
-
-/** Type of etm_task_p3_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio12_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio12_en:1;
-        /** etm_task_gpio12_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio12_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio13_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio13_en:1;
-        /** etm_task_gpio13_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio13_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio14_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio14_en:1;
-        /** etm_task_gpio14_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio14_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio15_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio15_en:1;
-        /** etm_task_gpio15_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio15_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p3_cfg_reg_t;
-
-/** Type of etm_task_p4_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio16_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio16_en:1;
-        /** etm_task_gpio16_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio16_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio17_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio17_en:1;
-        /** etm_task_gpio17_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio17_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio18_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio18_en:1;
-        /** etm_task_gpio18_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio18_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio19_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio19_en:1;
-        /** etm_task_gpio19_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio19_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p4_cfg_reg_t;
-
-/** Type of etm_task_p5_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio20_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio20_en:1;
-        /** etm_task_gpio20_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio20_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio21_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio21_en:1;
-        /** etm_task_gpio21_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio21_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio22_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio22_en:1;
-        /** etm_task_gpio22_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio22_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio23_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio23_en:1;
-        /** etm_task_gpio23_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio23_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p5_cfg_reg_t;
-
-/** Type of etm_task_p6_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio24_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio24_en:1;
-        /** etm_task_gpio24_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio24_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio25_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio25_en:1;
-        /** etm_task_gpio25_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio25_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio26_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio26_en:1;
-        /** etm_task_gpio26_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio26_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio27_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio27_en:1;
-        /** etm_task_gpio27_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio27_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p6_cfg_reg_t;
-
-/** Type of etm_task_p7_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio28_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio28_en:1;
-        /** etm_task_gpio28_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio28_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio29_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio29_en:1;
-        /** etm_task_gpio29_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio29_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio30_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio30_en:1;
-        /** etm_task_gpio30_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio30_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio31_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio31_en:1;
-        /** etm_task_gpio31_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio31_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p7_cfg_reg_t;
-
-/** Type of etm_task_p8_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio32_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio32_en:1;
-        /** etm_task_gpio32_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio32_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio33_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio33_en:1;
-        /** etm_task_gpio33_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio33_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio34_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio34_en:1;
-        /** etm_task_gpio34_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio34_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio35_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio35_en:1;
-        /** etm_task_gpio35_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio35_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p8_cfg_reg_t;
-
-/** Type of etm_task_p9_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio36_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio36_en:1;
-        /** etm_task_gpio36_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio36_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio37_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio37_en:1;
-        /** etm_task_gpio37_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio37_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio38_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio38_en:1;
-        /** etm_task_gpio38_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio38_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio39_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio39_en:1;
-        /** etm_task_gpio39_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio39_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p9_cfg_reg_t;
-
-/** Type of etm_task_p10_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio40_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio40_en:1;
-        /** etm_task_gpio40_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio40_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio41_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio41_en:1;
-        /** etm_task_gpio41_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio41_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio42_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio42_en:1;
-        /** etm_task_gpio42_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio42_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio43_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio43_en:1;
-        /** etm_task_gpio43_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio43_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p10_cfg_reg_t;
-
-/** Type of etm_task_p11_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio44_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio44_en:1;
-        /** etm_task_gpio44_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio44_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio45_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio45_en:1;
-        /** etm_task_gpio45_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio45_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio46_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio46_en:1;
-        /** etm_task_gpio46_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio46_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio47_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio47_en:1;
-        /** etm_task_gpio47_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio47_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p11_cfg_reg_t;
-
-/** Type of etm_task_p12_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio48_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio48_en:1;
-        /** etm_task_gpio48_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio48_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio49_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio49_en:1;
-        /** etm_task_gpio49_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio49_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio50_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio50_en:1;
-        /** etm_task_gpio50_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio50_sel:3;
-        uint32_t reserved_20:4;
-        /** etm_task_gpio51_en : R/W; bitpos: [24]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio51_en:1;
-        /** etm_task_gpio51_sel : R/W; bitpos: [27:25]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio51_sel:3;
-        uint32_t reserved_28:4;
-    };
-    uint32_t val;
-} gpio_etm_task_p12_cfg_reg_t;
-
-/** Type of etm_task_p13_cfg register
- *  Etm Configure Register to decide which GPIO been chosen
- */
-typedef union {
-    struct {
-        /** etm_task_gpio52_en : R/W; bitpos: [0]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio52_en:1;
-        /** etm_task_gpio52_sel : R/W; bitpos: [3:1]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio52_sel:3;
-        uint32_t reserved_4:4;
-        /** etm_task_gpio53_en : R/W; bitpos: [8]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio53_en:1;
-        /** etm_task_gpio53_sel : R/W; bitpos: [11:9]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio53_sel:3;
-        uint32_t reserved_12:4;
-        /** etm_task_gpio54_en : R/W; bitpos: [16]; default: 0;
-         *  Enable bit of GPIO response etm task.
-         */
-        uint32_t etm_task_gpio54_en:1;
-        /** etm_task_gpio54_sel : R/W; bitpos: [19:17]; default: 0;
-         *  GPIO choose a etm task channel.
-         */
-        uint32_t etm_task_gpio54_sel:3;
-        uint32_t reserved_20:12;
-    };
-    uint32_t val;
-} gpio_etm_task_p13_cfg_reg_t;
-
 
 /** Group: Version Register */
 /** Type of version register
@@ -727,13 +148,12 @@ typedef union {
         /** gpio_ext_date : R/W; bitpos: [27:0]; default: 35663952;
          *  Version control register.
          */
-        uint32_t gpio_ext_date:28;
+        uint32_t gpio_ext_date: 28;
-        uint32_t reserved_28:4;
+        uint32_t reserved_28: 4;
     };
     uint32_t val;
 } gpio_ext_version_reg_t;
 
-
 typedef struct gpio_sd_dev_t {
     volatile gpio_sigmadelta_chn_reg_t channel[8];
     uint32_t reserved_020;
@@ -747,20 +167,7 @@ typedef struct gpio_glitch_filter_dev_t {
 typedef struct gpio_etm_dev_t {
     volatile gpio_etm_event_chn_cfg_reg_t etm_event_chn_cfg[8];
     uint32_t reserved_080[8];
-    volatile gpio_etm_task_p0_cfg_reg_t etm_task_p0_cfg;
+    volatile gpio_etm_task_pn_cfg_reg_t etm_task_pn_cfg[14];
-    volatile gpio_etm_task_p1_cfg_reg_t etm_task_p1_cfg;
-    volatile gpio_etm_task_p2_cfg_reg_t etm_task_p2_cfg;
-    volatile gpio_etm_task_p3_cfg_reg_t etm_task_p3_cfg;
-    volatile gpio_etm_task_p4_cfg_reg_t etm_task_p4_cfg;
-    volatile gpio_etm_task_p5_cfg_reg_t etm_task_p5_cfg;
-    volatile gpio_etm_task_p6_cfg_reg_t etm_task_p6_cfg;
-    volatile gpio_etm_task_p7_cfg_reg_t etm_task_p7_cfg;
-    volatile gpio_etm_task_p8_cfg_reg_t etm_task_p8_cfg;
-    volatile gpio_etm_task_p9_cfg_reg_t etm_task_p9_cfg;
-    volatile gpio_etm_task_p10_cfg_reg_t etm_task_p10_cfg;
-    volatile gpio_etm_task_p11_cfg_reg_t etm_task_p11_cfg;
-    volatile gpio_etm_task_p12_cfg_reg_t etm_task_p12_cfg;
-    volatile gpio_etm_task_p13_cfg_reg_t etm_task_p13_cfg;
 } gpio_etm_dev_t;
 
 typedef struct {

components/soc/esp32p4/include/soc/soc_caps.h

@@ -36,7 +36,7 @@
 #define SOC_PCNT_SUPPORTED              1
 #define SOC_MCPWM_SUPPORTED             1
 // #define SOC_TWAI_SUPPORTED              1  //TODO: IDF-7470
-// #define SOC_ETM_SUPPORTED               1  //TODO: IDF-7478
+#define SOC_ETM_SUPPORTED               1
 // #define SOC_PARLIO_SUPPORTED            1  //TODO: IDF-7471, TODO: IDF-7472
 #define SOC_ASYNC_MEMCPY_SUPPORTED      1
 // disable usb serial jtag for esp32p4, current image does not support
@@ -162,7 +162,7 @@
 #define SOC_GDMA_NUM_GROUPS_MAX         2
 #define SOC_GDMA_PAIRS_PER_GROUP_MAX    3
 #define SOC_AXI_GDMA_SUPPORT_PSRAM      1
-// #define SOC_GDMA_SUPPORT_ETM            1  // Both AHB-DMA and AXI-DMA supports ETM  //TODO: IDF-7478
+// #define SOC_GDMA_SUPPORT_ETM            1
 
 /*-------------------------- ETM CAPS --------------------------------------*/
 #define SOC_ETM_GROUPS                  1U  // Number of ETM groups
@@ -177,7 +177,7 @@
 #define SOC_GPIO_SUPPORT_PIN_HYS_FILTER    1
 
 // GPIO peripheral has the ETM extension
-// #define SOC_GPIO_SUPPORT_ETM          1  //TODO: IDF-7841
+#define SOC_GPIO_SUPPORT_ETM          1
 #define SOC_GPIO_ETM_EVENTS_PER_GROUP 8
 #define SOC_GPIO_ETM_TASKS_PER_GROUP  8
 
@@ -408,6 +408,7 @@
 #define SOC_TIMER_GROUP_SUPPORT_XTAL      1
 #define SOC_TIMER_GROUP_SUPPORT_RC_FAST   1
 #define SOC_TIMER_GROUP_TOTAL_TIMERS      4
+#define SOC_TIMER_SUPPORT_ETM             1
 
 /*-------------------------- TWAI CAPS ---------------------------------------*/
 #define SOC_TWAI_CONTROLLER_NUM         2