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add esp32s2beta in soc component
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@@ -76,7 +76,7 @@ from low to high start address.
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*/
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const soc_memory_region_t soc_memory_regions[] = {
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#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
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{ 0x3F800000, 0x400000, 15, 0}, //SPI SRAM, if available
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{ SOC_EXTRAM_DATA_LOW, CONFIG_SPIRAM_SIZE, 15, 0}, //SPI SRAM, if available
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#endif
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{ 0x3FFAE000, 0x2000, 0, 0}, //pool 16 <- used for rom code
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{ 0x3FFB0000, 0x8000, 0, 0}, //pool 15 <- if BT is enabled, used as BT HW shared memory
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@@ -167,7 +167,7 @@ SOC_RESERVE_MEMORY_REGION(0x3fffc000, 0x40000000, trace_mem); //Reserve trace me
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#endif
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#ifdef CONFIG_ESP32_SPIRAM_SUPPORT
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SOC_RESERVE_MEMORY_REGION(0x3f800000, 0x3fC00000, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
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SOC_RESERVE_MEMORY_REGION(SOC_EXTRAM_DATA_LOW, SOC_EXTRAM_DATA_LOW + CONFIG_SPIRAM_SIZE, spi_ram); //SPI RAM gets added later if needed, in spiram.c; reserve it for now
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#endif
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#endif /* BOOTLOADER_BUILD */
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