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rmt: support esp32s3

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This commit is contained in:
chenjianqiang
2020-08-13 16:55:56 +08:00
committed by morris
parent 99fae0f0b5
commit 9465af0066
12 changed files with 2305 additions and 2827 deletions
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207
components/hal/esp32s3/include/hal/rmt_ll.h
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@@ -25,6 +25,10 @@ extern "C" {
#define RMT_LL_HW_BASE (&RMT)
#define RMT_LL_MEM_BASE (&RMTMEM)
#define RMT_LL_TX_CHAN_NUM (4)
#define RMT_LL_TX_CHAN_MASK (0x0F)
#define RMT_LL_RX_CHAN_MASK (0xF0)
static inline void rmt_ll_set_sclk(rmt_dev_t *dev, uint32_t source, uint32_t div_num, uint32_t div_frac_a, uint32_t div_frac_b)
{
dev->sys_conf.sclk_active = 0;
@@ -49,14 +53,18 @@ static inline void rmt_ll_reset_counter_clock_div(rmt_dev_t *dev, uint32_t chann
static inline void rmt_ll_reset_tx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 1;
dev->tx_conf[channel].mem_rd_rst = 0;
dev->tx_conf[channel].apb_mem_rst = 1;
dev->tx_conf[channel].apb_mem_rst = 0;
}
static inline void rmt_ll_reset_rx_pointer(rmt_dev_t *dev, uint32_t channel)
{
dev->rx_conf[channel].conf1.apb_mem_rst = 1;
dev->rx_conf[channel].conf1.mem_wr_rst = 1;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_wr_rst = 1;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_wr_rst = 0;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.apb_mem_rst = 1;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.apb_mem_rst = 0;
}
static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
@@ -67,10 +75,14 @@ static inline void rmt_ll_start_tx(rmt_dev_t *dev, uint32_t channel)
static inline void rmt_ll_stop_tx(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_conf[channel].tx_stop = 1;
dev->tx_conf[channel].conf_update = 1;
}
static inline void rmt_ll_enable_rx(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_en = enable;
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.conf_update = 1;
}
static inline void rmt_ll_power_down_mem(rmt_dev_t *dev, bool enable)
@@ -89,26 +101,35 @@ static inline bool rmt_ll_is_mem_power_down(rmt_dev_t *dev)
static inline void rmt_ll_set_mem_blocks(rmt_dev_t *dev, uint32_t channel, uint8_t block_num)
{
dev->tx_conf[channel].mem_size = block_num;
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].mem_size = block_num;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.mem_size = block_num;
}
}
static inline uint32_t rmt_ll_get_mem_blocks(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_conf[channel].mem_size) : (dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.mem_size);
}
static inline void rmt_ll_set_counter_clock_div(rmt_dev_t *dev, uint32_t channel, uint32_t div)
{
dev->tx_conf[channel].div_cnt = div;
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].div_cnt = div;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.div_cnt = div;
}
}
static inline uint32_t rmt_ll_get_counter_clock_div(rmt_dev_t *dev, uint32_t channel)
{
return dev->tx_conf[channel].div_cnt;
return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_conf[channel].div_cnt) : (dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.div_cnt);
}
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_enable_tx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->tx_conf[channel].mem_tx_wrap_en = enable;
}
static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
@@ -118,20 +139,24 @@ static inline void rmt_ll_enable_mem_access(rmt_dev_t *dev, bool enable)
static inline void rmt_ll_set_rx_idle_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.idle_thres = thres;
}
static inline uint32_t rmt_ll_get_rx_idle_thres(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.idle_thres;
}
static inline void rmt_ll_set_mem_owner(rmt_dev_t *dev, uint32_t channel, uint8_t owner)
{
if (channel >= RMT_LL_TX_CHAN_NUM) {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_owner = owner;
}
}
static inline uint32_t rmt_ll_get_mem_owner(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_owner;
}
static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -141,7 +166,7 @@ static inline void rmt_ll_enable_tx_loop(rmt_dev_t *dev, uint32_t channel, bool
static inline bool rmt_ll_is_tx_loop_enabled(rmt_dev_t *dev, uint32_t channel)
{
return false;
return dev->tx_conf[channel].tx_conti_mode;
}
static inline void rmt_ll_set_tx_loop_count(rmt_dev_t *dev, uint32_t channel, uint32_t count)
@@ -162,7 +187,7 @@ static inline void rmt_ll_enable_tx_loop_count(rmt_dev_t *dev, uint32_t channel,
static inline void rmt_ll_enable_tx_sync(rmt_dev_t *dev, bool enable)
{
dev->tx_sim.tx_sim_en = enable;
dev->tx_sim.en = enable;
}
static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
@@ -173,24 +198,30 @@ static inline void rmt_ll_add_channel_to_group(rmt_dev_t *dev, uint32_t channel)
static inline uint32_t rmt_ll_remove_channel_from_group(rmt_dev_t *dev, uint32_t channel)
{
dev->tx_sim.val &= ~(1 << channel);
return dev->tx_sim.val & 0x0F;
return dev->tx_sim.val & RMT_LL_TX_CHAN_MASK;
}
static inline void rmt_ll_enable_rx_filter(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_filter_en = enable;
}
static inline void rmt_ll_set_rx_filter_thres(rmt_dev_t *dev, uint32_t channel, uint32_t thres)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.rx_filter_thres = thres;
}
static inline void rmt_ll_set_counter_clock_src(rmt_dev_t *dev, uint32_t channel, uint8_t src)
{
dev->sys_conf.sclk_sel = src;
dev->sys_conf.sclk_div_num = 0;
dev->sys_conf.sclk_div_a = 0;
dev->sys_conf.sclk_div_b = 0;
}
static inline uint32_t rmt_ll_get_counter_clock_src(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->sys_conf.sclk_sel;
}
static inline void rmt_ll_enable_tx_idle(rmt_dev_t *dev, uint32_t channel, bool enable)
@@ -215,7 +246,7 @@ static inline uint32_t rmt_ll_get_tx_idle_level(rmt_dev_t *dev, uint32_t channel
static inline uint32_t rmt_ll_get_channel_status(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return (channel < RMT_LL_TX_CHAN_NUM) ? (dev->tx_status[channel].val) : (dev->rx_status[channel - RMT_LL_TX_CHAN_NUM].val);
}
static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
@@ -225,113 +256,148 @@ static inline void rmt_ll_set_tx_limit(rmt_dev_t *dev, uint32_t channel, uint32_
static inline void rmt_ll_set_rx_limit(rmt_dev_t *dev, uint32_t channel, uint32_t limit)
{
dev->rx_lim[channel - RMT_LL_TX_CHAN_NUM].rx_lim = limit;
}
static inline uint32_t rmt_ll_get_rx_limit(rmt_dev_t *dev, uint32_t channel)
{
return 0;
return dev->rx_lim[channel - RMT_LL_TX_CHAN_NUM].rx_lim;
}
static inline void rmt_ll_enable_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3));
dev->int_ena.val |= (enable << (channel * 3));
if (enable) {
dev->int_ena.val |= (BIT(0) << (channel));
} else {
dev->int_ena.val &= ~(BIT(0) << (channel));
}
}
static inline void rmt_ll_enable_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 1));
dev->int_ena.val |= (enable << (channel * 3 + 1));
if (enable) {
dev->int_ena.val |= (BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
} else {
dev->int_ena.val &= ~(BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
static inline void rmt_ll_enable_err_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel * 3 + 2));
dev->int_ena.val |= (enable << (channel * 3 + 2));
if(channel < RMT_LL_TX_CHAN_NUM) {
if (enable) {
dev->int_ena.val |= (BIT(4) << (channel));
} else {
dev->int_ena.val &= ~(BIT(4) << (channel));
}
} else {
if (enable) {
dev->int_ena.val |= (BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
} else {
dev->int_ena.val &= ~(BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
}
static inline void rmt_ll_enable_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 12));
dev->int_ena.val |= (enable << (channel + 12));
if (enable) {
dev->int_ena.val |= (BIT(8) << (channel));
} else {
dev->int_ena.val &= ~(BIT(8) << (channel));
}
}
static inline void rmt_ll_enable_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 16));
dev->int_ena.val |= (enable << (channel + 16));
if (enable) {
dev->int_ena.val |= (BIT(12) << (channel));
} else {
dev->int_ena.val &= ~(BIT(12) << (channel));
}
}
static inline void rmt_ll_enable_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->int_ena.val &= ~(1 << (channel + 20));
dev->int_ena.val |= (enable << (channel + 20));
if (enable) {
dev->int_ena.val |= (BIT(24) << (channel - RMT_LL_TX_CHAN_NUM));
} else {
dev->int_ena.val &= ~(BIT(24) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
static inline void rmt_ll_clear_tx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3));
dev->int_clr.val = (BIT(0) << (channel));
}
static inline void rmt_ll_clear_rx_end_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 1));
dev->int_clr.val = (BIT(16) << (channel - RMT_LL_TX_CHAN_NUM));
}
static inline void rmt_ll_clear_err_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel * 3 + 2));
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->int_clr.val = (BIT(4) << (channel));
} else {
dev->int_clr.val = (BIT(20) << (channel - RMT_LL_TX_CHAN_NUM));
}
}
static inline void rmt_ll_clear_tx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 12));
dev->int_clr.val = (BIT(8) << (channel));
}
static inline void rmt_ll_clear_tx_loop_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 16));
dev->int_clr.val = (BIT(12) << (channel));
}
static inline void rmt_ll_clear_rx_thres_interrupt(rmt_dev_t *dev, uint32_t channel)
{
dev->int_clr.val = (1 << (channel + 20));
dev->int_clr.val = (BIT(24) << (channel -RMT_LL_TX_CHAN_NUM));
}
static inline uint32_t rmt_ll_get_tx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x01) >> 0) | ((status & 0x08) >> 2) | ((status & 0x40) >> 4) | ((status & 0x200) >> 6);
return dev->int_st.val & RMT_LL_TX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_rx_end_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x02) >> 1) | ((status & 0x10) >> 3) | ((status & 0x80) >> 5) | ((status & 0x400) >> 7);
return (dev->int_st.val >> 12) & RMT_LL_RX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_tx_err_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 4) & RMT_LL_TX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_rx_err_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 16) & RMT_LL_RX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_err_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return ((status & 0x04) >> 2) | ((status & 0x20) >> 4) | ((status & 0x100) >> 6) | ((status & 0x800) >> 8);
return ((dev->int_st.val >> 4) & RMT_LL_TX_CHAN_MASK) | ((dev->int_st.val >> 16) & RMT_LL_RX_CHAN_MASK);
}
static inline uint32_t rmt_ll_get_tx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF000) >> 12;
}
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF0000) >> 16;
return (dev->int_st.val >> 8) & RMT_LL_TX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_rx_thres_interrupt_status(rmt_dev_t *dev)
{
uint32_t status = dev->int_st.val;
return (status & 0xF00000) >> 20;
return (dev->int_st.val >> 20) & RMT_LL_RX_CHAN_MASK;
}
static inline uint32_t rmt_ll_get_tx_loop_interrupt_status(rmt_dev_t *dev)
{
return (dev->int_st.val >> 12) & RMT_LL_TX_CHAN_MASK;
}
static inline void rmt_ll_set_tx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t high_ticks, uint32_t low_ticks)
@@ -349,21 +415,39 @@ static inline void rmt_ll_set_rx_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t
typeof(dev->rx_carrier[0]) reg;
reg.high_thres = high_ticks;
reg.low_thres = low_ticks;
dev->rx_carrier[channel].val = reg.val;
dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].val = reg.val;
}
static inline void rmt_ll_get_carrier_high_low_ticks(rmt_dev_t *dev, uint32_t channel, uint32_t *high_ticks, uint32_t *low_ticks)
{
if (channel < RMT_LL_TX_CHAN_NUM) {
*high_ticks = dev->tx_carrier[channel].high;
*low_ticks = dev->tx_carrier[channel].low;
} else {
*high_ticks = dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].high_thres;
*low_ticks = dev->rx_carrier[channel - RMT_LL_TX_CHAN_NUM].low_thres;
}
}
// This function has different meaning for TX and RX
// TX: enable to modulate carrier
// RX: enable to demodulate carrier
static inline void rmt_ll_enable_carrier(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->tx_conf[channel].carrier_en = enable;
if (channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].carrier_en = enable;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.carrier_en = enable;
}
}
static inline void rmt_ll_set_carrier_on_level(rmt_dev_t *dev, uint32_t channel, uint8_t level)
{
dev->tx_conf[channel].carrier_out_lv = level;
if (channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].carrier_out_lv = level;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf0.carrier_out_lv = level;
}
}
// set true, enable carrier in all RMT state (idle, reading, sending)
@@ -383,6 +467,23 @@ static inline void rmt_ll_write_memory(rmt_mem_t *mem, uint32_t channel, const r
static inline void rmt_ll_enable_rx_pingpong(rmt_dev_t *dev, uint32_t channel, bool enable)
{
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.mem_rx_wrap_en = enable;
}
static inline void rmt_write_fifo(rmt_dev_t *dev, uint32_t channel, const rmt_item32_t *data, uint32_t length)
{
for (uint32_t i = 0; i < length; i++) {
dev->data_ch[channel] = data[i].val;
}
}
static inline void rmt_ll_config_update(rmt_dev_t *dev, uint32_t channel)
{
if(channel < RMT_LL_TX_CHAN_NUM) {
dev->tx_conf[channel].conf_update = 1;
} else {
dev->rx_conf[channel - RMT_LL_TX_CHAN_NUM].conf1.conf_update = 1;
}
}
/************************************************************************************************