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https://github.com/espressif/esp-idf.git
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remove prefix and postfix
This commit is contained in:
Wangjialin
@@ -58,29 +58,29 @@ typedef volatile struct {
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}status_reg;
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union {
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struct {
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uint32_t time_out: 20; /*This register is used to configure the max clock number of receiving a data.*/
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uint32_t tout: 20; /*This register is used to configure the max clock number of receiving a data.*/
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uint32_t reserved20:12;
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};
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uint32_t val;
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}timeout;
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union {
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struct {
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uint32_t slave_addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
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uint32_t reserved15: 16;
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uint32_t addr_10bit_en: 1; /*This register is used to enable slave 10bit address mode.*/
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uint32_t addr: 15; /*when configured as i2c slave this register is used to configure slave's address.*/
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uint32_t reserved15: 16;
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uint32_t en_10bit: 1; /*This register is used to enable slave 10bit address mode.*/
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};
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uint32_t val;
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}slave_addr;
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union {
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struct {
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uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
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uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
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uint32_t rx_fifo_start_addr: 5; /*This is the offset address of the last receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t rx_fifo_end_addr: 5; /*This is the offset address of the first receiving data as described in nonfifo_rx_thres_register.*/
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uint32_t tx_fifo_start_addr: 5; /*This is the offset address of the first sending data as described in nonfifo_tx_thres register.*/
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uint32_t tx_fifo_end_addr: 5; /*This is the offset address of the last sending data as described in nonfifo_tx_thres register.*/
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uint32_t reserved20: 12;
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};
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uint32_t val;
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}rx_fifo_st;
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}fifo_st;
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union {
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struct {
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uint32_t rx_fifo_full_thrhd: 5;
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@@ -97,150 +97,150 @@ typedef volatile struct {
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}fifo_conf;
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union {
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struct {
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uint32_t fifo_rdata: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
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uint32_t data: 8; /*The register represent the byte data read from rx_fifo when use apb fifo access*/
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uint32_t reserved8: 24;
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};
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uint32_t val;
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}fifo_data;
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union {
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struct {
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uint32_t rx_fifo_full_int_raw: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
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uint32_t tx_fifo_empty_int_raw: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
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uint32_t rx_fifo_ovf_int_raw: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
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uint32_t end_detect_int_raw: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
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uint32_t slave_tran_comp_int_raw: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost_int_raw: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp_int_raw: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
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uint32_t trans_complete_int_raw: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
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uint32_t time_out_int_raw: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
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uint32_t trans_start_int_raw: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
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uint32_t ack_err_int_raw: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
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uint32_t rx_rec_full_int_raw: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty_int_raw: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
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uint32_t reserved13: 19;
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uint32_t rx_fifo_full: 1; /*The raw interrupt status bit for rx_fifo full when use apb fifo access.*/
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uint32_t tx_fifo_empty: 1; /*The raw interrupt status bit for tx_fifo empty when use apb fifo access.*/
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uint32_t rx_fifo_ovf: 1; /*The raw interrupt status bit for receiving data overflow when use apb fifo access.*/
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uint32_t end_detect: 1; /*The raw interrupt status bit for end_detect_int interrupt. when I2C deals with the END command it will produce end_detect_int interrupt.*/
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uint32_t slave_tran_comp: 1; /*The raw interrupt status bit for slave_tran_comp_int interrupt. when I2C Slave detects the STOP bit it will produce slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost: 1; /*The raw interrupt status bit for arbitration_lost_int interrupt.when I2C lost the usage right of I2C BUS it will produce arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp: 1; /*The raw interrupt status bit for master_tra_comp_int interrupt. when I2C Master sends or receives a byte it will produce master_tran_comp_int interrupt.*/
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uint32_t trans_complete: 1; /*The raw interrupt status bit for trans_complete_int interrupt. when I2C Master finished STOP command it will produce trans_complete_int interrupt.*/
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uint32_t time_out: 1; /*The raw interrupt status bit for time_out_int interrupt. when I2C takes a lot of time to receive a data it will produce time_out_int interrupt.*/
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uint32_t trans_start: 1; /*The raw interrupt status bit for trans_start_int interrupt. when I2C sends the START bit it will produce trans_start_int interrupt.*/
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uint32_t ack_err: 1; /*The raw interrupt status bit for ack_err_int interrupt. when I2C receives a wrong ACK bit it will produce ack_err_int interrupt..*/
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uint32_t rx_rec_full: 1; /*The raw interrupt status bit for rx_rec_full_int interrupt. when I2C receives more data than nonfifo_rx_thres it will produce rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty: 1; /*The raw interrupt status bit for tx_send_empty_int interrupt.when I2C sends more data than nonfifo_tx_thres it will produce tx_send_empty_int interrupt..*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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}int_raw;
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union {
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struct {
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uint32_t rx_fifo_full_int_clr: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
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uint32_t tx_fifo_empty_int_clr: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
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uint32_t rx_fifo_ovf_int_clr: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
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uint32_t end_detect_int_clr: 1; /*Set this bit to clear the end_detect_int interrupt.*/
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uint32_t slave_tran_comp_int_clr: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost_int_clr: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp_int_clr: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
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uint32_t trans_complete_int_clr: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
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uint32_t time_out_int_clr: 1; /*Set this bit to clear the time_out_int interrupt.*/
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uint32_t trans_start_int_clr: 1; /*Set this bit to clear the trans_start_int interrupt.*/
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uint32_t ack_err_int_clr: 1; /*Set this bit to clear the ack_err_int interrupt.*/
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uint32_t rx_rec_full_int_clr: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty_int_clr: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
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uint32_t reserved13: 19;
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uint32_t rx_fifo_full: 1; /*Set this bit to clear the rx_fifo_full_int interrupt.*/
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uint32_t tx_fifo_empty: 1; /*Set this bit to clear the tx_fifo_empty_int interrupt.*/
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uint32_t rx_fifo_ovf: 1; /*Set this bit to clear the rx_fifo_ovf_int interrupt.*/
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uint32_t end_detect: 1; /*Set this bit to clear the end_detect_int interrupt.*/
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uint32_t slave_tran_comp: 1; /*Set this bit to clear the slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost: 1; /*Set this bit to clear the arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp: 1; /*Set this bit to clear the master_tran_comp interrupt.*/
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uint32_t trans_complete: 1; /*Set this bit to clear the trans_complete_int interrupt.*/
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uint32_t time_out: 1; /*Set this bit to clear the time_out_int interrupt.*/
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uint32_t trans_start: 1; /*Set this bit to clear the trans_start_int interrupt.*/
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uint32_t ack_err: 1; /*Set this bit to clear the ack_err_int interrupt.*/
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uint32_t rx_rec_full: 1; /*Set this bit to clear the rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty: 1; /*Set this bit to clear the tx_send_empty_int interrupt.*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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}int_clr;
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union {
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struct {
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uint32_t rx_fifo_full_int_ena: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
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uint32_t tx_fifo_empty_int_ena: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
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uint32_t rx_fifo_ovf_int_ena: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
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uint32_t end_detect_int_ena: 1; /*The enable bit for end_detect_int interrupt.*/
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uint32_t slave_tran_comp_int_ena: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost_int_ena: 1; /*The enable bit for arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp_int_ena: 1; /*The enable bit for master_tran_comp_int interrupt.*/
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uint32_t trans_complete_int_ena: 1; /*The enable bit for trans_complete_int interrupt.*/
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uint32_t time_out_int_ena: 1; /*The enable bit for time_out_int interrupt.*/
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uint32_t trans_start_int_ena: 1; /*The enable bit for trans_start_int interrupt.*/
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uint32_t ack_err_int_ena: 1; /*The enable bit for ack_err_int interrupt.*/
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uint32_t rx_rec_full_int_ena: 1; /*The enable bit for rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty_int_ena: 1; /*The enable bit for tx_send_empty_int interrupt.*/
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uint32_t reserved13: 19;
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uint32_t rx_fifo_full: 1; /*The enable bit for rx_fifo_full_int interrupt.*/
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uint32_t tx_fifo_empty: 1; /*The enable bit for tx_fifo_empty_int interrupt.*/
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uint32_t rx_fifo_ovf: 1; /*The enable bit for rx_fifo_ovf_int interrupt.*/
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uint32_t end_detect: 1; /*The enable bit for end_detect_int interrupt.*/
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uint32_t slave_tran_comp: 1; /*The enable bit for slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost: 1; /*The enable bit for arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp: 1; /*The enable bit for master_tran_comp_int interrupt.*/
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uint32_t trans_complete: 1; /*The enable bit for trans_complete_int interrupt.*/
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uint32_t time_out: 1; /*The enable bit for time_out_int interrupt.*/
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uint32_t trans_start: 1; /*The enable bit for trans_start_int interrupt.*/
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uint32_t ack_err: 1; /*The enable bit for ack_err_int interrupt.*/
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uint32_t rx_rec_full: 1; /*The enable bit for rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty: 1; /*The enable bit for tx_send_empty_int interrupt.*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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}int_ena;
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union {
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struct {
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uint32_t rx_fifo_full_int_st: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
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uint32_t tx_fifo_empty_int_st: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
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uint32_t rx_fifo_ovf_int_st: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
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uint32_t end_detect_int_st: 1; /*The masked interrupt status for end_detect_int interrupt.*/
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uint32_t slave_tran_comp_int_st: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost_int_st: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp_int_st: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
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uint32_t trans_complete_int_st: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
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uint32_t time_out_int_st: 1; /*The masked interrupt status for time_out_int interrupt.*/
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uint32_t trans_start_int_st: 1; /*The masked interrupt status for trans_start_int interrupt.*/
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uint32_t ack_err_int_st: 1; /*The masked interrupt status for ack_err_int interrupt.*/
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uint32_t rx_rec_full_int_st: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty_int_st: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
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uint32_t reserved13: 19;
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uint32_t rx_fifo_full: 1; /*The masked interrupt status for rx_fifo_full_int interrupt.*/
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uint32_t tx_fifo_empty: 1; /*The masked interrupt status for tx_fifo_empty_int interrupt.*/
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uint32_t rx_fifo_ovf: 1; /*The masked interrupt status for rx_fifo_ovf_int interrupt.*/
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uint32_t end_detect: 1; /*The masked interrupt status for end_detect_int interrupt.*/
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uint32_t slave_tran_comp: 1; /*The masked interrupt status for slave_tran_comp_int interrupt.*/
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uint32_t arbitration_lost: 1; /*The masked interrupt status for arbitration_lost_int interrupt.*/
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uint32_t master_tran_comp: 1; /*The masked interrupt status for master_tran_comp_int interrupt.*/
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uint32_t trans_complete: 1; /*The masked interrupt status for trans_complete_int interrupt.*/
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uint32_t time_out: 1; /*The masked interrupt status for time_out_int interrupt.*/
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uint32_t trans_start: 1; /*The masked interrupt status for trans_start_int interrupt.*/
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uint32_t ack_err: 1; /*The masked interrupt status for ack_err_int interrupt.*/
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uint32_t rx_rec_full: 1; /*The masked interrupt status for rx_rec_full_int interrupt.*/
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uint32_t tx_send_empty: 1; /*The masked interrupt status for tx_send_empty_int interrupt.*/
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uint32_t reserved13: 19;
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};
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uint32_t val;
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}int_status;
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union {
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struct {
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uint32_t sda_hold_time:10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
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uint32_t reserved10: 22;
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uint32_t time: 10; /*This register is used to configure the clock num I2C used to hold the data after the negedge of SCL.*/
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uint32_t reserved10: 22;
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};
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uint32_t val;
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}sda_hold;
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union {
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struct {
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uint32_t sda_sample_time:10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
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uint32_t reserved10: 22;
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uint32_t time: 10; /*This register is used to configure the clock num I2C used to sample data on SDA after the posedge of SCL*/
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uint32_t reserved10: 22;
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};
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uint32_t val;
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}sda_sample;
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union {
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struct {
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uint32_t scl_high_period:14; /*This register is used to configure the clock num during SCL is low level.*/
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uint32_t reserved14: 18;
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uint32_t period: 14; /*This register is used to configure the clock num during SCL is low level.*/
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uint32_t reserved14: 18;
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};
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uint32_t val;
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}scl_high_period;
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uint32_t reserved_3c;
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union {
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struct {
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uint32_t scl_start_hold_time:10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
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uint32_t reserved10: 22;
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uint32_t time: 10; /*This register is used to configure the clock num between the negedge of SDA and negedge of SCL for start mark.*/
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uint32_t reserved10: 22;
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};
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uint32_t val;
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}scl_start_hold;
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union {
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struct {
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uint32_t scl_rstart_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
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uint32_t reserved10: 22;
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uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the negedge of SDA for restart mark.*/
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uint32_t reserved10: 22;
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};
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uint32_t val;
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}scl_rstart_setup;
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union {
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struct {
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uint32_t scl_stop_hold_time:14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
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uint32_t reserved14: 18;
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uint32_t time: 14; /*This register is used to configure the clock num after the STOP bit's posedge.*/
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uint32_t reserved14: 18;
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};
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uint32_t val;
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}scl_stop_hold;
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union {
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struct {
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uint32_t scl_stop_setup_time:10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
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uint32_t reserved10: 22;
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uint32_t time: 10; /*This register is used to configure the clock num between the posedge of SCL and the posedge of SDA.*/
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uint32_t reserved10: 22;
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};
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uint32_t val;
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}scl_stop_setup;
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union {
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struct {
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uint32_t scl_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
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uint32_t scl_filter_en: 1; /*This is the filter enable bit for SCL.*/
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uint32_t reserved4: 28;
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uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
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uint32_t en: 1; /*This is the filter enable bit for SCL.*/
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uint32_t reserved4: 28;
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};
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uint32_t val;
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}scl_filter_cfg;
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union {
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struct {
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uint32_t sda_filter_thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
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uint32_t sda_filter_en: 1; /*This is the filter enable bit for SDA.*/
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uint32_t reserved4: 28;
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uint32_t thres: 3; /*When input SCL's pulse width is smaller than this register value I2C ignores this pulse.*/
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uint32_t en: 1; /*This is the filter enable bit for SDA.*/
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uint32_t reserved4: 28;
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};
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uint32_t val;
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}sda_filter_cfg;
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@@ -252,7 +252,7 @@ typedef volatile struct {
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uint32_t ack_val: 1; /*ack_check_en ack_exp and ack value are used to control the ack bit.*/
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uint32_t op_code: 3; /*op_code is the command 0：RSTART 1：WRITE 2：READ 3：STOP . 4:END.*/
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uint32_t reserved14: 17;
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uint32_t command_done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
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uint32_t done: 1; /*When command0 is done in I2C Master mode this bit changes to high level.*/
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};
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uint32_t val;
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}command[16];
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Reference in New Issue
Block a user