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Merge branch 'feature/support_gpio_on_c61' into 'master'

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feat(gpio): support GPIO on ESP32C61

Closes IDF-9316

See merge request espressif/esp-idf!30380
This commit is contained in:
Kevin (Lao Kaiyao)
2024-04-25 11:00:32 +08:00
parent 4c0b3a501b 2c90b71d45
commit 95ab3ccf96
16 changed files with 367 additions and 1445 deletions
Download Patch File Download Diff File Expand all files Collapse all files

20
components/soc/esp32c61/include/soc/Kconfig.soc_caps.in
View File

@@ -161,7 +161,7 @@ config SOC_GPIO_PORT
config SOC_GPIO_PIN_COUNT
int
default 25
default 22
config SOC_GPIO_SUPPORT_RTC_INDEPENDENT
bool
@@ -181,7 +181,7 @@ config SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK
config SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK
hex
default 0x000000007FFFFF00
default 0x00000000003FFF80
config SOC_GPIO_SUPPORT_FORCE_HOLD
bool
@@ -567,22 +567,6 @@ config SOC_SHA_SUPPORT_SHA256
bool
default y
config SOC_SDM_GROUPS
int
default 1
config SOC_SDM_CHANNELS_PER_GROUP
int
default 4
config SOC_SDM_CLK_SUPPORT_PLL_F80M
bool
default y
config SOC_SDM_CLK_SUPPORT_XTAL
bool
default y
config SOC_SPI_PERIPH_NUM
int
default 2

4
components/soc/esp32c61/include/soc/gpio_num.h
View File

@@ -6,7 +6,6 @@
#pragma once
//TODO: [ESP32C61] IDF-9316, check pins attribute
#ifdef __cplusplus
extern "C" {
#endif
@@ -38,9 +37,6 @@ typedef enum {
GPIO_NUM_19 = 19, /*!< GPIO19, input and output */
GPIO_NUM_20 = 20, /*!< GPIO20, input and output */
GPIO_NUM_21 = 21, /*!< GPIO21, input and output */
GPIO_NUM_22 = 22, /*!< GPIO22, NC */
GPIO_NUM_23 = 23, /*!< GPIO23, NC */
GPIO_NUM_24 = 24, /*!< GPIO24, NC */
GPIO_NUM_MAX,
} gpio_num_t;

4
components/soc/esp32c61/include/soc/gpio_pins.h
View File

@@ -11,8 +11,8 @@
extern "C" {
#endif
#define GPIO_MATRIX_CONST_ONE_INPUT (0x38)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x3C)
#define GPIO_MATRIX_CONST_ONE_INPUT (0x20)
#define GPIO_MATRIX_CONST_ZERO_INPUT (0x30)
#ifdef __cplusplus
}

875
components/soc/esp32c61/include/soc/gpio_reg.h
View File

@@ -1844,517 +1844,6 @@ extern "C" {
#define GPIO_PIN21_INT_ENA_V 0x0000001FU
#define GPIO_PIN21_INT_ENA_S 13
/** GPIO_PIN22_REG register
* GPIO22 configuration register
*/
#define GPIO_PIN22_REG (DR_REG_GPIO_BASE + 0x11c)
/** GPIO_PIN22_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_M (GPIO_PIN22_SYNC2_BYPASS_V << GPIO_PIN22_SYNC2_BYPASS_S)
#define GPIO_PIN22_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC2_BYPASS_S 0
/** GPIO_PIN22_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN22_PAD_DRIVER (BIT(2))
#define GPIO_PIN22_PAD_DRIVER_M (GPIO_PIN22_PAD_DRIVER_V << GPIO_PIN22_PAD_DRIVER_S)
#define GPIO_PIN22_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN22_PAD_DRIVER_S 2
/** GPIO_PIN22_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN22_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_M (GPIO_PIN22_SYNC1_BYPASS_V << GPIO_PIN22_SYNC1_BYPASS_S)
#define GPIO_PIN22_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN22_SYNC1_BYPASS_S 3
/** GPIO_PIN22_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN22_INT_TYPE 0x00000007U
#define GPIO_PIN22_INT_TYPE_M (GPIO_PIN22_INT_TYPE_V << GPIO_PIN22_INT_TYPE_S)
#define GPIO_PIN22_INT_TYPE_V 0x00000007U
#define GPIO_PIN22_INT_TYPE_S 7
/** GPIO_PIN22_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN22_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN22_WAKEUP_ENABLE_M (GPIO_PIN22_WAKEUP_ENABLE_V << GPIO_PIN22_WAKEUP_ENABLE_S)
#define GPIO_PIN22_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN22_WAKEUP_ENABLE_S 10
/** GPIO_PIN22_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN22_INT_ENA 0x0000001FU
#define GPIO_PIN22_INT_ENA_M (GPIO_PIN22_INT_ENA_V << GPIO_PIN22_INT_ENA_S)
#define GPIO_PIN22_INT_ENA_V 0x0000001FU
#define GPIO_PIN22_INT_ENA_S 13
/** GPIO_PIN23_REG register
* GPIO23 configuration register
*/
#define GPIO_PIN23_REG (DR_REG_GPIO_BASE + 0x120)
/** GPIO_PIN23_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_M (GPIO_PIN23_SYNC2_BYPASS_V << GPIO_PIN23_SYNC2_BYPASS_S)
#define GPIO_PIN23_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC2_BYPASS_S 0
/** GPIO_PIN23_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN23_PAD_DRIVER (BIT(2))
#define GPIO_PIN23_PAD_DRIVER_M (GPIO_PIN23_PAD_DRIVER_V << GPIO_PIN23_PAD_DRIVER_S)
#define GPIO_PIN23_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN23_PAD_DRIVER_S 2
/** GPIO_PIN23_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN23_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_M (GPIO_PIN23_SYNC1_BYPASS_V << GPIO_PIN23_SYNC1_BYPASS_S)
#define GPIO_PIN23_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN23_SYNC1_BYPASS_S 3
/** GPIO_PIN23_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN23_INT_TYPE 0x00000007U
#define GPIO_PIN23_INT_TYPE_M (GPIO_PIN23_INT_TYPE_V << GPIO_PIN23_INT_TYPE_S)
#define GPIO_PIN23_INT_TYPE_V 0x00000007U
#define GPIO_PIN23_INT_TYPE_S 7
/** GPIO_PIN23_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN23_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN23_WAKEUP_ENABLE_M (GPIO_PIN23_WAKEUP_ENABLE_V << GPIO_PIN23_WAKEUP_ENABLE_S)
#define GPIO_PIN23_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN23_WAKEUP_ENABLE_S 10
/** GPIO_PIN23_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN23_INT_ENA 0x0000001FU
#define GPIO_PIN23_INT_ENA_M (GPIO_PIN23_INT_ENA_V << GPIO_PIN23_INT_ENA_S)
#define GPIO_PIN23_INT_ENA_V 0x0000001FU
#define GPIO_PIN23_INT_ENA_S 13
/** GPIO_PIN24_REG register
* GPIO24 configuration register
*/
#define GPIO_PIN24_REG (DR_REG_GPIO_BASE + 0x124)
/** GPIO_PIN24_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_M (GPIO_PIN24_SYNC2_BYPASS_V << GPIO_PIN24_SYNC2_BYPASS_S)
#define GPIO_PIN24_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC2_BYPASS_S 0
/** GPIO_PIN24_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN24_PAD_DRIVER (BIT(2))
#define GPIO_PIN24_PAD_DRIVER_M (GPIO_PIN24_PAD_DRIVER_V << GPIO_PIN24_PAD_DRIVER_S)
#define GPIO_PIN24_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN24_PAD_DRIVER_S 2
/** GPIO_PIN24_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN24_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_M (GPIO_PIN24_SYNC1_BYPASS_V << GPIO_PIN24_SYNC1_BYPASS_S)
#define GPIO_PIN24_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN24_SYNC1_BYPASS_S 3
/** GPIO_PIN24_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN24_INT_TYPE 0x00000007U
#define GPIO_PIN24_INT_TYPE_M (GPIO_PIN24_INT_TYPE_V << GPIO_PIN24_INT_TYPE_S)
#define GPIO_PIN24_INT_TYPE_V 0x00000007U
#define GPIO_PIN24_INT_TYPE_S 7
/** GPIO_PIN24_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN24_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN24_WAKEUP_ENABLE_M (GPIO_PIN24_WAKEUP_ENABLE_V << GPIO_PIN24_WAKEUP_ENABLE_S)
#define GPIO_PIN24_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN24_WAKEUP_ENABLE_S 10
/** GPIO_PIN24_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN24_INT_ENA 0x0000001FU
#define GPIO_PIN24_INT_ENA_M (GPIO_PIN24_INT_ENA_V << GPIO_PIN24_INT_ENA_S)
#define GPIO_PIN24_INT_ENA_V 0x0000001FU
#define GPIO_PIN24_INT_ENA_S 13
/** GPIO_PIN25_REG register
* GPIO25 configuration register
*/
#define GPIO_PIN25_REG (DR_REG_GPIO_BASE + 0x128)
/** GPIO_PIN25_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN25_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN25_SYNC2_BYPASS_M (GPIO_PIN25_SYNC2_BYPASS_V << GPIO_PIN25_SYNC2_BYPASS_S)
#define GPIO_PIN25_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN25_SYNC2_BYPASS_S 0
/** GPIO_PIN25_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN25_PAD_DRIVER (BIT(2))
#define GPIO_PIN25_PAD_DRIVER_M (GPIO_PIN25_PAD_DRIVER_V << GPIO_PIN25_PAD_DRIVER_S)
#define GPIO_PIN25_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN25_PAD_DRIVER_S 2
/** GPIO_PIN25_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN25_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN25_SYNC1_BYPASS_M (GPIO_PIN25_SYNC1_BYPASS_V << GPIO_PIN25_SYNC1_BYPASS_S)
#define GPIO_PIN25_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN25_SYNC1_BYPASS_S 3
/** GPIO_PIN25_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN25_INT_TYPE 0x00000007U
#define GPIO_PIN25_INT_TYPE_M (GPIO_PIN25_INT_TYPE_V << GPIO_PIN25_INT_TYPE_S)
#define GPIO_PIN25_INT_TYPE_V 0x00000007U
#define GPIO_PIN25_INT_TYPE_S 7
/** GPIO_PIN25_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN25_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN25_WAKEUP_ENABLE_M (GPIO_PIN25_WAKEUP_ENABLE_V << GPIO_PIN25_WAKEUP_ENABLE_S)
#define GPIO_PIN25_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN25_WAKEUP_ENABLE_S 10
/** GPIO_PIN25_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN25_INT_ENA 0x0000001FU
#define GPIO_PIN25_INT_ENA_M (GPIO_PIN25_INT_ENA_V << GPIO_PIN25_INT_ENA_S)
#define GPIO_PIN25_INT_ENA_V 0x0000001FU
#define GPIO_PIN25_INT_ENA_S 13
/** GPIO_PIN26_REG register
* GPIO26 configuration register
*/
#define GPIO_PIN26_REG (DR_REG_GPIO_BASE + 0x12c)
/** GPIO_PIN26_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN26_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN26_SYNC2_BYPASS_M (GPIO_PIN26_SYNC2_BYPASS_V << GPIO_PIN26_SYNC2_BYPASS_S)
#define GPIO_PIN26_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN26_SYNC2_BYPASS_S 0
/** GPIO_PIN26_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN26_PAD_DRIVER (BIT(2))
#define GPIO_PIN26_PAD_DRIVER_M (GPIO_PIN26_PAD_DRIVER_V << GPIO_PIN26_PAD_DRIVER_S)
#define GPIO_PIN26_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN26_PAD_DRIVER_S 2
/** GPIO_PIN26_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN26_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN26_SYNC1_BYPASS_M (GPIO_PIN26_SYNC1_BYPASS_V << GPIO_PIN26_SYNC1_BYPASS_S)
#define GPIO_PIN26_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN26_SYNC1_BYPASS_S 3
/** GPIO_PIN26_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN26_INT_TYPE 0x00000007U
#define GPIO_PIN26_INT_TYPE_M (GPIO_PIN26_INT_TYPE_V << GPIO_PIN26_INT_TYPE_S)
#define GPIO_PIN26_INT_TYPE_V 0x00000007U
#define GPIO_PIN26_INT_TYPE_S 7
/** GPIO_PIN26_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN26_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN26_WAKEUP_ENABLE_M (GPIO_PIN26_WAKEUP_ENABLE_V << GPIO_PIN26_WAKEUP_ENABLE_S)
#define GPIO_PIN26_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN26_WAKEUP_ENABLE_S 10
/** GPIO_PIN26_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN26_INT_ENA 0x0000001FU
#define GPIO_PIN26_INT_ENA_M (GPIO_PIN26_INT_ENA_V << GPIO_PIN26_INT_ENA_S)
#define GPIO_PIN26_INT_ENA_V 0x0000001FU
#define GPIO_PIN26_INT_ENA_S 13
/** GPIO_PIN27_REG register
* GPIO27 configuration register
*/
#define GPIO_PIN27_REG (DR_REG_GPIO_BASE + 0x130)
/** GPIO_PIN27_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN27_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN27_SYNC2_BYPASS_M (GPIO_PIN27_SYNC2_BYPASS_V << GPIO_PIN27_SYNC2_BYPASS_S)
#define GPIO_PIN27_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN27_SYNC2_BYPASS_S 0
/** GPIO_PIN27_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN27_PAD_DRIVER (BIT(2))
#define GPIO_PIN27_PAD_DRIVER_M (GPIO_PIN27_PAD_DRIVER_V << GPIO_PIN27_PAD_DRIVER_S)
#define GPIO_PIN27_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN27_PAD_DRIVER_S 2
/** GPIO_PIN27_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN27_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN27_SYNC1_BYPASS_M (GPIO_PIN27_SYNC1_BYPASS_V << GPIO_PIN27_SYNC1_BYPASS_S)
#define GPIO_PIN27_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN27_SYNC1_BYPASS_S 3
/** GPIO_PIN27_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN27_INT_TYPE 0x00000007U
#define GPIO_PIN27_INT_TYPE_M (GPIO_PIN27_INT_TYPE_V << GPIO_PIN27_INT_TYPE_S)
#define GPIO_PIN27_INT_TYPE_V 0x00000007U
#define GPIO_PIN27_INT_TYPE_S 7
/** GPIO_PIN27_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN27_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN27_WAKEUP_ENABLE_M (GPIO_PIN27_WAKEUP_ENABLE_V << GPIO_PIN27_WAKEUP_ENABLE_S)
#define GPIO_PIN27_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN27_WAKEUP_ENABLE_S 10
/** GPIO_PIN27_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN27_INT_ENA 0x0000001FU
#define GPIO_PIN27_INT_ENA_M (GPIO_PIN27_INT_ENA_V << GPIO_PIN27_INT_ENA_S)
#define GPIO_PIN27_INT_ENA_V 0x0000001FU
#define GPIO_PIN27_INT_ENA_S 13
/** GPIO_PIN28_REG register
* GPIO28 configuration register
*/
#define GPIO_PIN28_REG (DR_REG_GPIO_BASE + 0x134)
/** GPIO_PIN28_SYNC2_BYPASS : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN28_SYNC2_BYPASS 0x00000003U
#define GPIO_PIN28_SYNC2_BYPASS_M (GPIO_PIN28_SYNC2_BYPASS_V << GPIO_PIN28_SYNC2_BYPASS_S)
#define GPIO_PIN28_SYNC2_BYPASS_V 0x00000003U
#define GPIO_PIN28_SYNC2_BYPASS_S 0
/** GPIO_PIN28_PAD_DRIVER : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
#define GPIO_PIN28_PAD_DRIVER (BIT(2))
#define GPIO_PIN28_PAD_DRIVER_M (GPIO_PIN28_PAD_DRIVER_V << GPIO_PIN28_PAD_DRIVER_S)
#define GPIO_PIN28_PAD_DRIVER_V 0x00000001U
#define GPIO_PIN28_PAD_DRIVER_S 2
/** GPIO_PIN28_SYNC1_BYPASS : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
#define GPIO_PIN28_SYNC1_BYPASS 0x00000003U
#define GPIO_PIN28_SYNC1_BYPASS_M (GPIO_PIN28_SYNC1_BYPASS_V << GPIO_PIN28_SYNC1_BYPASS_S)
#define GPIO_PIN28_SYNC1_BYPASS_V 0x00000003U
#define GPIO_PIN28_SYNC1_BYPASS_S 3
/** GPIO_PIN28_INT_TYPE : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
#define GPIO_PIN28_INT_TYPE 0x00000007U
#define GPIO_PIN28_INT_TYPE_M (GPIO_PIN28_INT_TYPE_V << GPIO_PIN28_INT_TYPE_S)
#define GPIO_PIN28_INT_TYPE_V 0x00000007U
#define GPIO_PIN28_INT_TYPE_S 7
/** GPIO_PIN28_WAKEUP_ENABLE : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
#define GPIO_PIN28_WAKEUP_ENABLE (BIT(10))
#define GPIO_PIN28_WAKEUP_ENABLE_M (GPIO_PIN28_WAKEUP_ENABLE_V << GPIO_PIN28_WAKEUP_ENABLE_S)
#define GPIO_PIN28_WAKEUP_ENABLE_V 0x00000001U
#define GPIO_PIN28_WAKEUP_ENABLE_S 10
/** GPIO_PIN28_INT_ENA : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
#define GPIO_PIN28_INT_ENA 0x0000001FU
#define GPIO_PIN28_INT_ENA_M (GPIO_PIN28_INT_ENA_V << GPIO_PIN28_INT_ENA_S)
#define GPIO_PIN28_INT_ENA_V 0x0000001FU
#define GPIO_PIN28_INT_ENA_S 13
/** GPIO_FUNC0_IN_SEL_CFG_REG register
* Configuration register for input signal 0
*/
@@ -5293,370 +4782,6 @@ extern "C" {
#define GPIO_FUNC21_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC21_OE_INV_SEL_S 11
/** GPIO_FUNC22_OUT_SEL_CFG_REG register
* Configuration register for GPIO22 output
*/
#define GPIO_FUNC22_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb1c)
/** GPIO_FUNC22_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO22.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 22 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC22_OUT_SEL 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_M (GPIO_FUNC22_OUT_SEL_V << GPIO_FUNC22_OUT_SEL_S)
#define GPIO_FUNC22_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC22_OUT_SEL_S 0
/** GPIO_FUNC22_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC22_OUT_INV_SEL_M (GPIO_FUNC22_OUT_INV_SEL_V << GPIO_FUNC22_OUT_INV_SEL_S)
#define GPIO_FUNC22_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OUT_INV_SEL_S 9
/** GPIO_FUNC22_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 22 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC22_OE_SEL (BIT(10))
#define GPIO_FUNC22_OE_SEL_M (GPIO_FUNC22_OE_SEL_V << GPIO_FUNC22_OE_SEL_S)
#define GPIO_FUNC22_OE_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_SEL_S 10
/** GPIO_FUNC22_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC22_OE_INV_SEL (BIT(11))
#define GPIO_FUNC22_OE_INV_SEL_M (GPIO_FUNC22_OE_INV_SEL_V << GPIO_FUNC22_OE_INV_SEL_S)
#define GPIO_FUNC22_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC22_OE_INV_SEL_S 11
/** GPIO_FUNC23_OUT_SEL_CFG_REG register
* Configuration register for GPIO23 output
*/
#define GPIO_FUNC23_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb20)
/** GPIO_FUNC23_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO23.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 23 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC23_OUT_SEL 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_M (GPIO_FUNC23_OUT_SEL_V << GPIO_FUNC23_OUT_SEL_S)
#define GPIO_FUNC23_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC23_OUT_SEL_S 0
/** GPIO_FUNC23_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC23_OUT_INV_SEL_M (GPIO_FUNC23_OUT_INV_SEL_V << GPIO_FUNC23_OUT_INV_SEL_S)
#define GPIO_FUNC23_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OUT_INV_SEL_S 9
/** GPIO_FUNC23_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 23 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC23_OE_SEL (BIT(10))
#define GPIO_FUNC23_OE_SEL_M (GPIO_FUNC23_OE_SEL_V << GPIO_FUNC23_OE_SEL_S)
#define GPIO_FUNC23_OE_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_SEL_S 10
/** GPIO_FUNC23_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC23_OE_INV_SEL (BIT(11))
#define GPIO_FUNC23_OE_INV_SEL_M (GPIO_FUNC23_OE_INV_SEL_V << GPIO_FUNC23_OE_INV_SEL_S)
#define GPIO_FUNC23_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC23_OE_INV_SEL_S 11
/** GPIO_FUNC24_OUT_SEL_CFG_REG register
* Configuration register for GPIO24 output
*/
#define GPIO_FUNC24_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb24)
/** GPIO_FUNC24_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO24.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit 24 of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC24_OUT_SEL 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_M (GPIO_FUNC24_OUT_SEL_V << GPIO_FUNC24_OUT_SEL_S)
#define GPIO_FUNC24_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC24_OUT_SEL_S 0
/** GPIO_FUNC24_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC24_OUT_INV_SEL_M (GPIO_FUNC24_OUT_INV_SEL_V << GPIO_FUNC24_OUT_INV_SEL_S)
#define GPIO_FUNC24_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OUT_INV_SEL_S 9
/** GPIO_FUNC24_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit 24 of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC24_OE_SEL (BIT(10))
#define GPIO_FUNC24_OE_SEL_M (GPIO_FUNC24_OE_SEL_V << GPIO_FUNC24_OE_SEL_S)
#define GPIO_FUNC24_OE_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_SEL_S 10
/** GPIO_FUNC24_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC24_OE_INV_SEL (BIT(11))
#define GPIO_FUNC24_OE_INV_SEL_M (GPIO_FUNC24_OE_INV_SEL_V << GPIO_FUNC24_OE_INV_SEL_S)
#define GPIO_FUNC24_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC24_OE_INV_SEL_S 11
/** GPIO_FUNC25_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC25_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb28)
/** GPIO_FUNC25_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC25_OUT_SEL 0x000001FFU
#define GPIO_FUNC25_OUT_SEL_M (GPIO_FUNC25_OUT_SEL_V << GPIO_FUNC25_OUT_SEL_S)
#define GPIO_FUNC25_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC25_OUT_SEL_S 0
/** GPIO_FUNC25_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC25_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC25_OUT_INV_SEL_M (GPIO_FUNC25_OUT_INV_SEL_V << GPIO_FUNC25_OUT_INV_SEL_S)
#define GPIO_FUNC25_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC25_OUT_INV_SEL_S 9
/** GPIO_FUNC25_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC25_OE_SEL (BIT(10))
#define GPIO_FUNC25_OE_SEL_M (GPIO_FUNC25_OE_SEL_V << GPIO_FUNC25_OE_SEL_S)
#define GPIO_FUNC25_OE_SEL_V 0x00000001U
#define GPIO_FUNC25_OE_SEL_S 10
/** GPIO_FUNC25_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC25_OE_INV_SEL (BIT(11))
#define GPIO_FUNC25_OE_INV_SEL_M (GPIO_FUNC25_OE_INV_SEL_V << GPIO_FUNC25_OE_INV_SEL_S)
#define GPIO_FUNC25_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC25_OE_INV_SEL_S 11
/** GPIO_FUNC26_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC26_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb2c)
/** GPIO_FUNC26_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC26_OUT_SEL 0x000001FFU
#define GPIO_FUNC26_OUT_SEL_M (GPIO_FUNC26_OUT_SEL_V << GPIO_FUNC26_OUT_SEL_S)
#define GPIO_FUNC26_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC26_OUT_SEL_S 0
/** GPIO_FUNC26_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC26_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC26_OUT_INV_SEL_M (GPIO_FUNC26_OUT_INV_SEL_V << GPIO_FUNC26_OUT_INV_SEL_S)
#define GPIO_FUNC26_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC26_OUT_INV_SEL_S 9
/** GPIO_FUNC26_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC26_OE_SEL (BIT(10))
#define GPIO_FUNC26_OE_SEL_M (GPIO_FUNC26_OE_SEL_V << GPIO_FUNC26_OE_SEL_S)
#define GPIO_FUNC26_OE_SEL_V 0x00000001U
#define GPIO_FUNC26_OE_SEL_S 10
/** GPIO_FUNC26_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC26_OE_INV_SEL (BIT(11))
#define GPIO_FUNC26_OE_INV_SEL_M (GPIO_FUNC26_OE_INV_SEL_V << GPIO_FUNC26_OE_INV_SEL_S)
#define GPIO_FUNC26_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC26_OE_INV_SEL_S 11
/** GPIO_FUNC27_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC27_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb30)
/** GPIO_FUNC27_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC27_OUT_SEL 0x000001FFU
#define GPIO_FUNC27_OUT_SEL_M (GPIO_FUNC27_OUT_SEL_V << GPIO_FUNC27_OUT_SEL_S)
#define GPIO_FUNC27_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC27_OUT_SEL_S 0
/** GPIO_FUNC27_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC27_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC27_OUT_INV_SEL_M (GPIO_FUNC27_OUT_INV_SEL_V << GPIO_FUNC27_OUT_INV_SEL_S)
#define GPIO_FUNC27_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC27_OUT_INV_SEL_S 9
/** GPIO_FUNC27_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC27_OE_SEL (BIT(10))
#define GPIO_FUNC27_OE_SEL_M (GPIO_FUNC27_OE_SEL_V << GPIO_FUNC27_OE_SEL_S)
#define GPIO_FUNC27_OE_SEL_V 0x00000001U
#define GPIO_FUNC27_OE_SEL_S 10
/** GPIO_FUNC27_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC27_OE_INV_SEL (BIT(11))
#define GPIO_FUNC27_OE_INV_SEL_M (GPIO_FUNC27_OE_INV_SEL_V << GPIO_FUNC27_OE_INV_SEL_S)
#define GPIO_FUNC27_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC27_OE_INV_SEL_S 11
/** GPIO_FUNC28_OUT_SEL_CFG_REG register
* Configuration register for GPIO$n output
*/
#define GPIO_FUNC28_OUT_SEL_CFG_REG (DR_REG_GPIO_BASE + 0xb34)
/** GPIO_FUNC28_OUT_SEL : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
#define GPIO_FUNC28_OUT_SEL 0x000001FFU
#define GPIO_FUNC28_OUT_SEL_M (GPIO_FUNC28_OUT_SEL_V << GPIO_FUNC28_OUT_SEL_S)
#define GPIO_FUNC28_OUT_SEL_V 0x000001FFU
#define GPIO_FUNC28_OUT_SEL_S 0
/** GPIO_FUNC28_OUT_INV_SEL : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC28_OUT_INV_SEL (BIT(9))
#define GPIO_FUNC28_OUT_INV_SEL_M (GPIO_FUNC28_OUT_INV_SEL_V << GPIO_FUNC28_OUT_INV_SEL_S)
#define GPIO_FUNC28_OUT_INV_SEL_V 0x00000001U
#define GPIO_FUNC28_OUT_INV_SEL_S 9
/** GPIO_FUNC28_OE_SEL : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
#define GPIO_FUNC28_OE_SEL (BIT(10))
#define GPIO_FUNC28_OE_SEL_M (GPIO_FUNC28_OE_SEL_V << GPIO_FUNC28_OE_SEL_S)
#define GPIO_FUNC28_OE_SEL_V 0x00000001U
#define GPIO_FUNC28_OE_SEL_S 10
/** GPIO_FUNC28_OE_INV_SEL : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
#define GPIO_FUNC28_OE_INV_SEL (BIT(11))
#define GPIO_FUNC28_OE_INV_SEL_M (GPIO_FUNC28_OE_INV_SEL_V << GPIO_FUNC28_OE_INV_SEL_S)
#define GPIO_FUNC28_OE_INV_SEL_V 0x00000001U
#define GPIO_FUNC28_OE_INV_SEL_S 11
/** GPIO_CLOCK_GATE_REG register
* GPIO clock gate register
*/

444
components/soc/esp32c61/include/soc/gpio_struct.h
View File

@@ -330,254 +330,6 @@ typedef union {
uint32_t val;
} gpio_pinn_reg_t;
/** Type of pin25 register
* GPIO25 configuration register
*/
typedef union {
struct {
/** pin25_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin25_sync2_bypass:2;
/** pin25_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin25_pad_driver:1;
/** pin25_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin25_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin25_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin25_int_type:3;
/** pin25_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin25_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin25_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin25_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin25_reg_t;
/** Type of pin26 register
* GPIO26 configuration register
*/
typedef union {
struct {
/** pin26_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin26_sync2_bypass:2;
/** pin26_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin26_pad_driver:1;
/** pin26_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin26_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin26_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin26_int_type:3;
/** pin26_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin26_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin26_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin26_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin26_reg_t;
/** Type of pin27 register
* GPIO27 configuration register
*/
typedef union {
struct {
/** pin27_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin27_sync2_bypass:2;
/** pin27_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin27_pad_driver:1;
/** pin27_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin27_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin27_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin27_int_type:3;
/** pin27_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin27_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin27_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin27_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin27_reg_t;
/** Type of pin28 register
* GPIO28 configuration register
*/
typedef union {
struct {
/** pin28_sync2_bypass : R/W; bitpos: [1:0]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the second-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin28_sync2_bypass:2;
/** pin28_pad_driver : R/W; bitpos: [2]; default: 0;
* Configures to select pin drive mode. \\
* 0: Normal output\\
* 1: Open drain output \\
*/
uint32_t pin28_pad_driver:1;
/** pin28_sync1_bypass : R/W; bitpos: [4:3]; default: 0;
* Configures whether or not to synchronize GPIO input data on either edge of IO MUX
* operating clock for the first-level synchronization.\\
* 0: Not synchronize\\
* 1: Synchronize on falling edge\\
* 2: Synchronize on rising edge\\
* 3: Synchronize on rising edge\\
*/
uint32_t pin28_sync1_bypass:2;
uint32_t reserved_5:2;
/** pin28_int_type : R/W; bitpos: [9:7]; default: 0;
* Configures GPIO interrupt type.\\
* 0: GPIO interrupt disabled\\
* 1: Rising edge trigger\\
* 2: Falling edge trigger\\
* 3: Any edge trigger\\
* 4: Low level trigger\\
* 5: High level trigger\\
*/
uint32_t pin28_int_type:3;
/** pin28_wakeup_enable : R/W; bitpos: [10]; default: 0;
* Configures whether or not to enable GPIO wake-up function.\\
* 0: Disable\\
* 1: Enable\\
* This function only wakes up the CPU from Light-sleep. \\
*/
uint32_t pin28_wakeup_enable:1;
uint32_t reserved_11:2;
/** pin28_int_ena : R/W; bitpos: [17:13]; default: 0;
* Configures whether or not to enable CPU interrupt.
*
* - bit13: Configures whether or not to enable CPU interrupt:\\
* 0: Disable\\
* 1: Enable\\
* - bit14 ~ bit17: invalid
*/
uint32_t pin28_int_ena:5;
uint32_t reserved_18:14;
};
uint32_t val;
} gpio_pin28_reg_t;
/** Group: Input Configuration Registers */
/** Type of func0_in_sel_cfg register
@@ -661,186 +413,6 @@ typedef union {
uint32_t val;
} gpio_funcn_out_sel_cfg_reg_t;
/** Type of func25_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func25_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func25_out_sel:9;
/** func25_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func25_out_inv_sel:1;
/** func25_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func25_oe_sel:1;
/** func25_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func25_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func25_out_sel_cfg_reg_t;
/** Type of func26_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func26_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func26_out_sel:9;
/** func26_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func26_out_inv_sel:1;
/** func26_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func26_oe_sel:1;
/** func26_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func26_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func26_out_sel_cfg_reg_t;
/** Type of func27_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func27_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func27_out_sel:9;
/** func27_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func27_out_inv_sel:1;
/** func27_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func27_oe_sel:1;
/** func27_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func27_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func27_out_sel_cfg_reg_t;
/** Type of func28_out_sel_cfg register
* Configuration register for GPIO$n output
*/
typedef union {
struct {
/** func28_out_sel : R/W/SC; bitpos: [8:0]; default: 256;
* Configures to select a signal $Y (0 <= $Y < 256) from 256 peripheral signals to be
* output from GPIO$n.\\
* 0: Select signal 0\\
* 1: Select signal 1\\
* ......\\
* 254: Select signal 254\\
* 255: Select signal 255\\
* Or\\
* 256: Bit $n of GPIO_OUT_REG and GPIO_ENABLE_REG are selected as the output value
* and output enable.
*
* For the detailed signal list, see Table <a
* href=tab:iomuxgpio-periph-signals-via-gpio-matrix">link</a>.
* "
*/
uint32_t func28_out_sel:9;
/** func28_out_inv_sel : R/W/SC; bitpos: [9]; default: 0;
* Configures whether or not to invert the output value.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func28_out_inv_sel:1;
/** func28_oe_sel : R/W; bitpos: [10]; default: 0;
* Configures to select the source of output enable signal.\\
* 0: Use output enable signal from peripheral.\\
* 1: Force the output enable signal to be sourced from bit $n of GPIO_ENABLE_REG. \\
*/
uint32_t func28_oe_sel:1;
/** func28_oe_inv_sel : R/W; bitpos: [11]; default: 0;
* Configures whether or not to invert the output enable signal.\\
* 0: Not invert\\
* 1: Invert\\
*/
uint32_t func28_oe_inv_sel:1;
uint32_t reserved_12:20;
};
uint32_t val;
} gpio_func28_out_sel_cfg_reg_t;
/** Group: Clock Gate Register */
/** Type of clock_gate register
@@ -896,20 +468,12 @@ typedef struct {
uint32_t reserved_0a8[3];
volatile gpio_status_next_reg_t status_next;
uint32_t reserved_0b8[3];
volatile gpio_pinn_reg_t pinn[25];
volatile gpio_pin25_reg_t pin25;
volatile gpio_pin26_reg_t pin26;
volatile gpio_pin27_reg_t pin27;
volatile gpio_pin28_reg_t pin28;
uint32_t reserved_138[99];
volatile gpio_pinn_reg_t pinn[22]; // 0-21 are fanned out, 22-24 are not fanned out but padded out, 25-28 are not padded out. Only 0-21 are available.
uint32_t reserved_11c[106];
volatile gpio_func_in_sel_cfg_reg_t func_in_sel_cfg[256]; //0-255. reserved: 1-5, 18-26, 36-40, 44-45, 48-63, 70-71, 75-81, 84-96, 101-117, 122-255;
uint32_t reserved_4ac[256];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[25];
volatile gpio_func25_out_sel_cfg_reg_t func25_out_sel_cfg;
volatile gpio_func26_out_sel_cfg_reg_t func26_out_sel_cfg;
volatile gpio_func27_out_sel_cfg_reg_t func27_out_sel_cfg;
volatile gpio_func28_out_sel_cfg_reg_t func28_out_sel_cfg;
uint32_t reserved_b38[176];
volatile gpio_funcn_out_sel_cfg_reg_t funcn_out_sel_cfg[22];
uint32_t reserved_b1c[183];
volatile gpio_clock_gate_reg_t clock_gate;
volatile gpio_date_reg_t date;
} gpio_dev_t;

26
components/soc/esp32c61/include/soc/io_mux_reg.h
View File

@@ -117,9 +117,6 @@ extern "C" {
#define IO_MUX_GPIO19_REG PERIPHS_IO_MUX_U_PAD_SPIHD
#define IO_MUX_GPIO20_REG PERIPHS_IO_MUX_U_PAD_SPICLK
#define IO_MUX_GPIO21_REG PERIPHS_IO_MUX_U_PAD_SPID
#define IO_MUX_GPIO22_REG PERIPHS_IO_MUX_U_PAD_GPIO22
#define IO_MUX_GPIO23_REG PERIPHS_IO_MUX_U_PAD_GPIO23
#define IO_MUX_GPIO24_REG PERIPHS_IO_MUX_U_PAD_GPIO24
#define PIN_FUNC_GPIO 1
@@ -137,13 +134,16 @@ extern "C" {
#define SPI_D_GPIO_NUM 21
#define SPI_Q_GPIO_NUM 16
#define USB_INT_PHY0_DM_GPIO_NUM 12
#define USB_INT_PHY0_DP_GPIO_NUM 13
#define MAX_RTC_GPIO_NUM 7
#define MAX_PAD_GPIO_NUM 30
#define MAX_GPIO_NUM 34
#define MAX_PAD_GPIO_NUM 21
#define MAX_GPIO_NUM 28
#define HIGH_IO_HOLD_BIT_SHIFT 32
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define REG_IO_MUX_BASE DR_REG_IO_MUX_BASE
#define PIN_CTRL (REG_IO_MUX_BASE +0x00)
#define PAD_POWER_SEL BIT(15)
#define PAD_POWER_SEL_V 0x1
#define PAD_POWER_SEL_M BIT(15)
@@ -277,18 +277,6 @@ extern "C" {
#define FUNC_SPID_GPIO21 1
#define FUNC_SPID_SPID 0
#define PERIPHS_IO_MUX_U_PAD_GPIO22 (REG_IO_MUX_BASE + 0x58)
#define FUNC_GPIO22_GPIO22 1
#define FUNC_GPIO22_GPIO22_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO23 (REG_IO_MUX_BASE + 0x5C)
#define FUNC_GPIO23_GPIO23 1
#define FUNC_GPIO23_GPIO23_0 0
#define PERIPHS_IO_MUX_U_PAD_GPIO24 (REG_IO_MUX_BASE + 0x60)
#define FUNC_GPIO24_GPIO24 1
#define FUNC_GPIO24_GPIO24_0 0
/** IO_MUX_DATE_REG register
* Version control register
*/

6
components/soc/esp32c61/include/soc/io_mux_struct.h
View File

@@ -129,12 +129,12 @@ typedef union {
typedef struct {
volatile io_mux_gpion_reg_t gpion[25];
uint32_t reserved_064[102];
volatile io_mux_gpion_reg_t gpion[22];
uint32_t reserved_058[105];
volatile io_mux_date_reg_t date;
} io_mux_dev_t;
extern io_mux_dev_t IO_MUX;
extern io_mux_dev_t IOMUX;
#ifndef __cplusplus
_Static_assert(sizeof(io_mux_dev_t) == 0x200, "Invalid size of io_mux_dev_t structure");

16
components/soc/esp32c61/include/soc/soc_caps.h
View File

@@ -36,7 +36,6 @@
#define SOC_RTC_FAST_MEM_SUPPORTED 1
#define SOC_RTC_MEM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9274
// #define SOC_I2S_SUPPORTED 1 //TODO: [ESP32C61] IDF-9312, IDF-9313
// #define SOC_SDM_SUPPORTED 1 //TODO: [ESP32C61] IDF-9335
// #define SOC_GPSPI_SUPPORTED 1 //TODO: [ESP32C61] IDF-9299, IDF-9300, IDF-9301
// #define SOC_LEDC_SUPPORTED 1 //TODO: [ESP32C61] IDF-9291
// #define SOC_I2C_SUPPORTED 1 //TODO: [ESP32C61] IDF-9296, IDF-9297
@@ -181,9 +180,8 @@
/*-------------------------- GPIO CAPS ---------------------------------------*/
// ESP32-C61 has 1 GPIO peripheral
#define SOC_GPIO_PORT 1U
#define SOC_GPIO_PIN_COUNT 25
#define SOC_GPIO_PIN_COUNT 22
// #define SOC_GPIO_SUPPORT_PIN_GLITCH_FILTER 1 //TODO: [ESP32C61] IDF-9340
// #define SOC_GPIO_FLEX_GLITCH_FILTER_NUM 8 //TODO: [ESP32C61] IDF-9340
// GPIO peripheral has the ETM extension
// #define SOC_GPIO_SUPPORT_ETM 1 //TODO: [ESP32C61] IDF-9340
@@ -200,10 +198,10 @@
#define SOC_GPIO_IN_RANGE_MAX 21
#define SOC_GPIO_OUT_RANGE_MAX 21
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6 | BIT7)
#define SOC_GPIO_DEEP_SLEEP_WAKE_VALID_GPIO_MASK (0ULL | BIT0 | BIT1 | BIT2 | BIT3 | BIT4 | BIT5 | BIT6)
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_8~GPIO_NUM_30)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x000000007FFFFF00ULL
// digital I/O pad powered by VDD3P3_CPU or VDD_SPI(GPIO_NUM_7~GPIO_NUM_21)
#define SOC_GPIO_VALID_DIGITAL_IO_PAD_MASK 0x00000000003FFF80ULL
// Support to force hold all IOs
#define SOC_GPIO_SUPPORT_FORCE_HOLD (1)
@@ -367,12 +365,6 @@
#define SOC_SHA_SUPPORT_SHA224 (1)
#define SOC_SHA_SUPPORT_SHA256 (1)
/*-------------------------- Sigma Delta Modulator CAPS -----------------*/
#define SOC_SDM_GROUPS 1U
#define SOC_SDM_CHANNELS_PER_GROUP 4
#define SOC_SDM_CLK_SUPPORT_PLL_F80M 1
#define SOC_SDM_CLK_SUPPORT_XTAL 1
/*-------------------------- SPI CAPS ----------------------------------------*/
#define SOC_SPI_PERIPH_NUM 2
#define SOC_SPI_PERIPH_CS_NUM(i) 6