bootloader, esp32: add workaround for Tensilica erratum 572

If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.

components/soc/esp32/include/soc/cpu.h

@@ -19,6 +19,7 @@
 #include <stdbool.h>
 #include <stddef.h>
 #include "xtensa/corebits.h"
+#include "xtensa/config/core.h"
 
 /* C macros for xtensa special register read/write/exchange */
 
@@ -51,6 +52,14 @@ static inline void cpu_write_itlb(unsigned vpn, unsigned attr)
     asm volatile ("witlb  %1, %0; isync\n" :: "r" (vpn), "r" (attr));
 }
 
+static inline void cpu_init_memctl()
+{
+#if XCHAL_ERRATUM_572
+    uint32_t memctl = XCHAL_CACHE_MEMCTL_DEFAULT;
+    WSR(MEMCTL, memctl);
+#endif // XCHAL_ERRATUM_572
+}
+
 /**
  * @brief Configure memory region protection
  *