mirror of
https://github.com/espressif/esp-idf.git
synced 2025-08-23 17:24:44 +00:00
Merge branch 'feature/i2c_master_new_driver' into 'master'
I2C: Add new i2c master impl APIs and i2c eeprom example See merge request espressif/esp-idf!23592
This commit is contained in:
C.S.M
@@ -17,6 +17,7 @@
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#include "soc/pcr_struct.h"
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#include "hal/i2c_types.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/lp_clkrst_struct.h"
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#ifdef __cplusplus
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extern "C" {
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@@ -27,13 +28,13 @@ extern "C" {
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*/
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typedef union {
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struct {
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uint32_t byte_num: 8,
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ack_en: 1,
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ack_exp: 1,
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ack_val: 1,
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op_code: 3,
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reserved14: 17,
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done: 1;
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uint32_t byte_num: 8, /*!< Specifies the length of data (in bytes) to be read or written */
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ack_en: 1, /*!< Used to enable the I2C controller during a write operation to check whether ACK */
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ack_exp: 1, /*!< Used to configure the level of the ACK bit expected by the I2C controller during a write operation */
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ack_val: 1, /*!< Used to configure the level of the ACK bit sent by the I2C controller during a read operation */
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op_code: 3, /*!< Indicates the command */
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reserved14: 17, /*!< Reserved bits */
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done: 1; /*!< Indicates that a command has been executed */
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};
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uint32_t val;
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} i2c_ll_hw_cmd_t;
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@@ -46,25 +47,32 @@ typedef union {
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#define I2C_LL_CMD_END 4 /*!<I2C end command */
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typedef enum {
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I2C_INTR_NACK = (1 << 10),
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I2C_INTR_TIMEOUT = (1 << 8),
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I2C_INTR_MST_COMPLETE = (1 << 7),
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I2C_INTR_ARBITRATION = (1 << 5),
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I2C_INTR_END_DETECT = (1 << 3),
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I2C_INTR_ST_TO = (1 << 13),
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} i2c_ll_master_intr_t;
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I2C_LL_INTR_TXFIFO_WM = (1 << 1),
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I2C_LL_INTR_RXFIFO_WM = (1 << 0),
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I2C_LL_INTR_NACK = (1 << 10),
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I2C_LL_INTR_TIMEOUT = (1 << 8),
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I2C_LL_INTR_MST_COMPLETE = (1 << 7),
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I2C_LL_INTR_ARBITRATION = (1 << 5),
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I2C_LL_INTR_END_DETECT = (1 << 3),
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I2C_LL_INTR_ST_TO = (1 << 13),
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I2C_LL_INTR_START = (1 << 15),
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I2C_LL_INTR_STRETCH = (1 << 16),
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I2C_LL_INTR_UNMATCH = (1 << 18),
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} i2c_ll_intr_t;
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typedef enum {
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I2C_INTR_TXFIFO_WM = (1 << 1),
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I2C_INTR_RXFIFO_WM = (1 << 0),
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I2C_INTR_SLV_COMPLETE = (1 << 7),
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I2C_INTR_START = (1 << 15),
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} i2c_ll_slave_intr_t;
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I2C_LL_STRETCH_REASON_MASTER_START = 0,
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I2C_LL_STRETCH_REASON_TX_EMPTY = 1,
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I2C_LL_STRETCH_REASON_RX_FULL = 2,
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} i2c_ll_stretch_cause_t;
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// Get the I2C hardware instance
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#define I2C_LL_GET_HW(i2c_num) (((i2c_num) == I2C_NUM_0) ? (&I2C0) : (&LP_I2C))
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#define I2C_LL_MASTER_EVENT_INTR (I2C_NACK_INT_ENA_M|I2C_TIME_OUT_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_ARBITRATION_LOST_INT_ENA_M|I2C_END_DETECT_INT_ENA_M)
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#define I2C_LL_SLAVE_EVENT_INTR (I2C_RXFIFO_WM_INT_ENA_M|I2C_TRANS_COMPLETE_INT_ENA_M|I2C_TXFIFO_WM_INT_ENA_M)
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#define I2C_LL_SLAVE_EVENT_INTR (I2C_TRANS_COMPLETE_INT_ENA_M|I2C_TXFIFO_WM_INT_ENA_M|I2C_RXFIFO_WM_INT_ENA_M | I2C_SLAVE_STRETCH_INT_ENA_M | I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M)
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#define I2C_LL_SLAVE_RX_EVENT_INTR (I2C_TRANS_COMPLETE_INT_ENA_M | I2C_RXFIFO_WM_INT_ENA_M | I2C_SLAVE_STRETCH_INT_ENA_M | I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M)
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#define I2C_LL_SLAVE_TX_EVENT_INTR (I2C_TXFIFO_WM_INT_ENA_M | I2C_SLAVE_ADDR_UNMATCH_INT_ENA_M)
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#define I2C_LL_RESET_SLV_SCL_PULSE_NUM_DEFAULT (9)
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/**
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* @brief Calculate I2C bus frequency
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@@ -78,7 +86,7 @@ typedef enum {
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*
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* @return None
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*/
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static inline void i2c_ll_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal)
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static inline void i2c_ll_master_cal_bus_clk(uint32_t source_clk, uint32_t bus_freq, i2c_hal_clk_config_t *clk_cal)
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{
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uint32_t clkm_div = source_clk / (bus_freq * 1024) +1;
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uint32_t sclk_freq = source_clk / clkm_div;
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@@ -125,7 +133,7 @@ static inline void i2c_ll_update(i2c_dev_t *hw)
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*
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* @return None
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*/
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static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg)
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static inline void i2c_ll_master_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bus_cfg)
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{
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2c_sclk_conf, i2c_sclk_div_num, bus_cfg->clkm_div - 1);
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@@ -153,6 +161,20 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bu
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hw->to.time_out_en = 1;
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}
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/**
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* @brief Set fractional divider
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*
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* @param hw Beginning address of the peripheral registers
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* @param div_a The denominator of the frequency divider factor of the i2c function clock
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* @param div_b The numerator of the frequency divider factor of the i2c function clock.
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*/
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static inline void i2c_ll_master_set_fractional_divider(i2c_dev_t *hw, uint8_t div_a, uint8_t div_b)
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{
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/* Set div_a and div_b to 0, as it's not necessary to use them */
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2c_sclk_conf, i2c_sclk_div_a, div_a);
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HAL_FORCE_MODIFY_U32_REG_FIELD(PCR.i2c_sclk_conf, i2c_sclk_div_b, div_b);
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}
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/**
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* @brief Reset I2C txFIFO
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*
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@@ -160,6 +182,7 @@ static inline void i2c_ll_set_bus_timing(i2c_dev_t *hw, i2c_hal_clk_config_t *bu
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_txfifo_rst(i2c_dev_t *hw)
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{
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hw->fifo_conf.tx_fifo_rst = 1;
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@@ -173,28 +196,13 @@ static inline void i2c_ll_txfifo_rst(i2c_dev_t *hw)
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_rxfifo_rst(i2c_dev_t *hw)
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{
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hw->fifo_conf.rx_fifo_rst = 1;
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hw->fifo_conf.rx_fifo_rst = 0;
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}
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/**
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* @brief Configure I2C SCL timing
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*
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* @param hw Beginning address of the peripheral registers
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* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
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* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
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*
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* @return None.
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*/
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static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period)
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{
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hw->scl_low_period.scl_low_period = low_period - 1;
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hw->scl_high_period.scl_high_period = hight_period - 10;
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hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period;
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}
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/**
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* @brief Clear I2C interrupt status
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*
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@@ -217,6 +225,7 @@ static inline void i2c_ll_clear_intr_mask(i2c_dev_t *hw, uint32_t mask)
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*
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_enable_intr_mask(i2c_dev_t *hw, uint32_t mask)
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{
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hw->int_ena.val |= mask;
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@@ -257,7 +266,7 @@ static inline void i2c_ll_get_intr_mask(i2c_dev_t *hw, uint32_t *intr_status)
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*
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* @return None
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*/
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static inline void i2c_ll_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
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static inline void i2c_ll_slave_set_fifo_mode(i2c_dev_t *hw, bool fifo_mode_en)
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{
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hw->fifo_conf.nonfifo_en = fifo_mode_en ? 0 : 1;
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}
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@@ -275,6 +284,19 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
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hw->to.time_out_value = tout;
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}
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/**
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* @brief Configure I2C slave broadcasting mode.
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*
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* @param hw Beginning address of the peripheral registers
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* @param broadcast_en Set true to enable broadcast, else, set it false
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*
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* @return None
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*/
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static inline void i2c_ll_slave_broadcast_enable(i2c_dev_t *hw, bool broadcast_en)
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{
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hw->ctr.addr_broadcasting_en = broadcast_en;
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}
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/**
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* @brief Configure I2C slave address
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*
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@@ -286,8 +308,15 @@ static inline void i2c_ll_set_tout(i2c_dev_t *hw, int tout)
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*/
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static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, bool addr_10bit_en)
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{
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hw->slave_addr.slave_addr = slave_addr;
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hw->slave_addr.addr_10bit_en = addr_10bit_en;
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if (addr_10bit_en) {
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uint8_t addr_14_7 = (slave_addr & 0xff) << 7;
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uint8_t addr_6_0 = ((slave_addr & 0x300) >> 8) | 0x78;
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hw->slave_addr.slave_addr = addr_14_7 | addr_6_0;
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hw->ctr.addr_10bit_rw_check_en = addr_10bit_en;
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} else {
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hw->slave_addr.slave_addr = slave_addr;
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}
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}
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/**
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@@ -300,7 +329,7 @@ static inline void i2c_ll_set_slave_addr(i2c_dev_t *hw, uint16_t slave_addr, boo
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
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static inline void i2c_ll_master_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int cmd_idx)
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{
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hw->command[cmd_idx].val = cmd.val;
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}
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@@ -314,7 +343,7 @@ static inline void i2c_ll_write_cmd_reg(i2c_dev_t *hw, i2c_ll_hw_cmd_t cmd, int
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*
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* @return None
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*/
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static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
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static inline void i2c_ll_master_set_start_timing(i2c_dev_t *hw, int start_setup, int start_hold)
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{
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hw->scl_rstart_setup.scl_rstart_setup_time = start_setup;
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hw->scl_start_hold.scl_start_hold_time = start_hold - 1;
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@@ -329,7 +358,7 @@ static inline void i2c_ll_set_start_timing(i2c_dev_t *hw, int start_setup, int s
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*
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* @return None
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*/
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static inline void i2c_ll_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold)
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static inline void i2c_ll_master_set_stop_timing(i2c_dev_t *hw, int stop_setup, int stop_hold)
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{
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hw->scl_stop_setup.scl_stop_setup_time = stop_setup;
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hw->scl_stop_hold.scl_stop_hold_time = stop_hold;
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@@ -391,21 +420,6 @@ static inline void i2c_ll_set_data_mode(i2c_dev_t *hw, i2c_trans_mode_t tx_mode,
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hw->ctr.rx_lsb_first = rx_mode;
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}
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/**
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* @brief Get the I2C data mode
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*
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* @param hw Beginning address of the peripheral registers
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* @param tx_mode Pointer to accept the received bytes mode
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* @param rx_mode Pointer to accept the sended bytes mode
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*
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* @return None
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*/
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static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
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{
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*tx_mode = hw->ctr.tx_lsb_first;
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*rx_mode = hw->ctr.rx_lsb_first;
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}
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/**
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* @brief Get I2C sda timing configuration
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*
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@@ -440,6 +454,7 @@ static inline uint32_t i2c_ll_get_hw_version(i2c_dev_t *hw)
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*
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* @return True if I2C state machine is busy, else false will be returned
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*/
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__attribute__((always_inline))
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static inline bool i2c_ll_is_bus_busy(i2c_dev_t *hw)
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{
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return hw->sr.bus_busy;
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@@ -503,7 +518,7 @@ static inline void i2c_ll_get_tout(i2c_dev_t *hw, int *timeout)
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* @return None
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*/
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__attribute__((always_inline))
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static inline void i2c_ll_trans_start(i2c_dev_t *hw)
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static inline void i2c_ll_master_trans_start(i2c_dev_t *hw)
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{
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hw->ctr.trans_start = 1;
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}
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@@ -538,21 +553,6 @@ static inline void i2c_ll_get_stop_timing(i2c_dev_t *hw, int *setup_time, int *h
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*hold_time = hw->scl_stop_hold.scl_stop_hold_time;
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}
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/**
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* @brief Get I2C SCL timing configuration
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*
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* @param hw Beginning address of the peripheral registers
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* @param high_period Pointer to accept the SCL high period
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* @param low_period Pointer to accept the SCL low period
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*
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* @return None
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*/
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static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period)
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{
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*high_period = hw->scl_high_period.scl_high_period + hw->scl_high_period.scl_wait_high_period;
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*low_period = hw->scl_low_period.scl_low_period + 1;
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}
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/**
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* @brief Write the I2C hardware txFIFO
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*
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@@ -587,6 +587,56 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
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}
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}
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/**
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* @brief Write the I2C hardware txFIFO
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*
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* @param hw Beginning address of the peripheral registers
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* @param ram_offset Offset value of I2C RAM.
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* @param ptr Pointer to data buffer
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* @param len Amount of data needs to be writen
|
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*
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* @return None.
|
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*/
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static inline void i2c_ll_write_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, const uint8_t *ptr, uint8_t len)
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{
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uint32_t *fifo_addr = (uint32_t *)&hw->txfifo_start_addr;
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for (int i = 0; i < len; i++) {
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fifo_addr[i + ram_offset] = ptr[i];
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}
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}
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/**
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* @brief Read the I2C hardware ram
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*
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* @param hw Beginning address of the peripheral registers
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* @param ram_offset Offset value of I2C RAM.
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* @param ptr Pointer to data buffer
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* @param len Amount of data needs read
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*
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* @return None
|
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*/
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static inline void i2c_ll_read_by_nonfifo(i2c_dev_t *hw, uint8_t ram_offset, uint8_t *ptr, uint8_t len)
|
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{
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uint32_t *fifo_addr = (uint32_t *)&hw->rxfifo_start_addr;
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for (int i = 0; i < len; i++) {
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ptr[i] = fifo_addr[i + ram_offset];
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}
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}
|
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|
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/**
|
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* @brief Get access to I2C RAM address directly
|
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*
|
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* @param hw Beginning address of the peripheral registers
|
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* @param addr_wr_en Enable I2C ram address read and write
|
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*
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* @return None
|
||||
*/
|
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static inline void i2c_ll_enable_mem_access_nonfifo(i2c_dev_t *hw, bool addr_wr_en)
|
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{
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hw->fifo_conf.fifo_addr_cfg_en = addr_wr_en;
|
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}
|
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|
||||
/**
|
||||
* @brief Configure I2C hardware filter
|
||||
*
|
||||
@@ -596,7 +646,7 @@ static inline void i2c_ll_read_rxfifo(i2c_dev_t *hw, uint8_t *ptr, uint8_t len)
|
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*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
|
||||
static inline void i2c_ll_master_set_filter(i2c_dev_t *hw, uint8_t filter_num)
|
||||
{
|
||||
if (filter_num > 0) {
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hw->filter_cfg.scl_filter_thres = filter_num;
|
||||
@@ -616,7 +666,7 @@ static inline void i2c_ll_set_filter(i2c_dev_t *hw, uint8_t filter_num)
|
||||
*
|
||||
* @return The hardware filter configuration
|
||||
*/
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||||
static inline void i2c_ll_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
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||||
static inline void i2c_ll_master_get_filter(i2c_dev_t *hw, uint8_t *filter_conf)
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||||
{
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||||
*filter_conf = hw->filter_cfg.scl_filter_thres;
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||||
}
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||||
@@ -641,12 +691,13 @@ static inline void i2c_ll_master_fsm_rst(i2c_dev_t *hw)
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||||
* Note: The master cannot detect if deadlock happens, but when the scl_st_to interrupt is generated, a deadlock may occur.
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||||
*
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||||
* @param hw Beginning address of the peripheral registers
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||||
* @param slave_pulses When I2C master is IDLE, the number of pulses will be sent out.
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||||
*
|
||||
* @return None
|
||||
*/
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||||
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw)
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||||
static inline void i2c_ll_master_clr_bus(i2c_dev_t *hw, uint32_t slave_pulses)
|
||||
{
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||||
hw->scl_sp_conf.scl_rst_slv_num = 9;
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||||
hw->scl_sp_conf.scl_rst_slv_num = slave_pulses;
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||||
hw->scl_sp_conf.scl_rst_slv_en = 1;
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||||
hw->ctr.conf_upgate = 1;
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||||
// hardward will clear scl_rst_slv_en after sending SCL pulses,
|
||||
@@ -758,6 +809,28 @@ static inline volatile void *i2c_ll_get_interrupt_status_reg(i2c_dev_t *dev)
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
* @brief Enable I2C slave clock stretch.
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers.
|
||||
* @param enable true: Enable, false: Disable.
|
||||
*/
|
||||
static inline void i2c_ll_slave_enable_scl_stretch(i2c_dev_t *dev, bool enable)
|
||||
{
|
||||
dev->scl_stretch_conf.slave_scl_stretch_en = enable;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Clear I2C clock stretch status
|
||||
*
|
||||
* @param dev Beginning address of the peripheral registers
|
||||
*/
|
||||
__attribute__((always_inline))
|
||||
static inline void i2c_ll_slave_clear_stretch(i2c_dev_t *dev)
|
||||
{
|
||||
dev->scl_stretch_conf.slave_scl_stretch_clr = 1;
|
||||
}
|
||||
|
||||
//////////////////////////////////////////Deprecated Functions//////////////////////////////////////////////////////////
|
||||
/////////////////////////////The following functions are only used by the legacy driver/////////////////////////////////
|
||||
/////////////////////////////They might be removed in the next major release (ESP-IDF 6.0)//////////////////////////////
|
||||
@@ -975,6 +1048,52 @@ static inline void i2c_ll_slave_disable_rx_it(i2c_dev_t *hw)
|
||||
hw->int_ena.val &= (~I2C_LL_SLAVE_RX_INT);
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Configure I2C SCL timing
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param hight_period The I2C SCL hight period (in core clock cycle, hight_period > 2)
|
||||
* @param low_period The I2C SCL low period (in core clock cycle, low_period > 1)
|
||||
*
|
||||
* @return None.
|
||||
*/
|
||||
static inline void i2c_ll_set_scl_timing(i2c_dev_t *hw, int hight_period, int low_period)
|
||||
{
|
||||
hw->scl_low_period.scl_low_period = low_period - 1;
|
||||
hw->scl_high_period.scl_high_period = hight_period - 10;
|
||||
hw->scl_high_period.scl_wait_high_period = hight_period - hw->scl_high_period.scl_high_period;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get the I2C data mode
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param tx_mode Pointer to accept the received bytes mode
|
||||
* @param rx_mode Pointer to accept the sended bytes mode
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_get_data_mode(i2c_dev_t *hw, i2c_trans_mode_t *tx_mode, i2c_trans_mode_t *rx_mode)
|
||||
{
|
||||
*tx_mode = hw->ctr.tx_lsb_first;
|
||||
*rx_mode = hw->ctr.rx_lsb_first;
|
||||
}
|
||||
|
||||
/**
|
||||
* @brief Get I2C SCL timing configuration
|
||||
*
|
||||
* @param hw Beginning address of the peripheral registers
|
||||
* @param high_period Pointer to accept the SCL high period
|
||||
* @param low_period Pointer to accept the SCL low period
|
||||
*
|
||||
* @return None
|
||||
*/
|
||||
static inline void i2c_ll_get_scl_timing(i2c_dev_t *hw, int *high_period, int *low_period)
|
||||
{
|
||||
*high_period = hw->scl_high_period.scl_high_period + hw->scl_high_period.scl_wait_high_period;
|
||||
*low_period = hw->scl_low_period.scl_low_period + 1;
|
||||
}
|
||||
|
||||
#ifdef __cplusplus
|
||||
}
|
||||
#endif
|
||||
|
||||
Reference in New Issue
Block a user