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feat(isp): isp af submodule low level driver

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This commit is contained in:
Armando
2023-10-17 18:54:13 +08:00
parent 7c21207bd3
commit 97526e9288
10 changed files with 1000 additions and 2 deletions
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16
components/soc/esp32p4/include/soc/Kconfig.soc_caps.in
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@@ -555,6 +555,22 @@ config SOC_I2S_TDM_FULL_DATA_WIDTH
bool
default y
config SOC_ISP_NUMS
int
default 1
config SOC_ISP_AF_CTRLR_NUMS
int
default 1
config SOC_ISP_AF_ENV_DETECTOR_NUMS
int
default 1
config SOC_ISP_AF_WINDOW_NUMS
int
default 3
config SOC_LEDC_SUPPORT_PLL_DIV_CLOCK
bool
default y

17
components/soc/esp32p4/include/soc/clk_tree_defs.h
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@@ -443,6 +443,23 @@ typedef enum {
FLASH_CLK_SRC_SPLL = SOC_MOD_CLK_SPLL, /*!< Select SOC_MOD_CLK_SPLL as FLASH source clock */
} soc_periph_flash_clk_src_t;
/////////////////////////////////////////////////ISP////////////////////////////////////////////////////////////////////
/**
* @brief Array initializer for all supported clock sources of ISP
*/
#define SOC_ISP_CLKS {SOC_MOD_CLK_XTAL, SOC_MOD_CLK_PLL_F160M, SOC_MOD_CLK_PLL_F240M}
/**
* @brief Type of ISP clock source.
*/
typedef enum {
ISP_CLK_SRC_DEFAULT = SOC_MOD_CLK_PLL_F160M, /*!< Select SOC_MOD_CLK_PLL_F160M as ISP source clock */
ISP_CLK_SRC_XTAL = SOC_MOD_CLK_XTAL, /*!< Select SOC_MOD_CLK_XTAL as ISP source clock */
ISP_CLK_SRC_PLL160 = SOC_MOD_CLK_PLL_F160M, /*!< Select SOC_MOD_CLK_PLL_F160M as ISP source clock */
ISP_CLK_SRC_PLL240 = SOC_MOD_CLK_PLL_F240M, /*!< Select SOC_MOD_CLK_PLL_F240M as ISP source clock */
} soc_periph_isp_clk_src_t;
//////////////////////////////////////////////////SDM//////////////////////////////////////////////////////////////
//////////////////////////////////////////////////GPIO Glitch Filter////////////////////////////////////////////////////

5
components/soc/esp32p4/include/soc/isp_struct.h
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@@ -247,11 +247,11 @@ typedef union {
*/
uint32_t bayer_mode:2;
/** hsync_start_exist : R/W; bitpos: [29]; default: 1;
* this bit configures the line end packet exist or not. 0: not exist, 1: exist
* this bit configures the line end start exist or not. 0: not exist, 1: exist
*/
uint32_t hsync_start_exist:1;
/** hsync_end_exist : R/W; bitpos: [30]; default: 1;
* this bit configures the line start packet exist or not. 0: not exist, 1: exist
* this bit configures the line end packet exist or not. 0: not exist, 1: exist
*/
uint32_t hsync_end_exist:1;
uint32_t reserved_31:1;
@@ -3857,6 +3857,7 @@ typedef struct {
volatile isp_rdn_eco_high_reg_t rdn_eco_high;
} isp_dev_t;
extern isp_dev_t ISP;
#ifndef __cplusplus
_Static_assert(sizeof(isp_dev_t) == 0x244, "Invalid size of isp_dev_t structure");

6
components/soc/esp32p4/include/soc/soc_caps.h
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@@ -267,6 +267,12 @@
#define SOC_I2S_PDM_MAX_RX_LINES (4) // On I2S0
#define SOC_I2S_TDM_FULL_DATA_WIDTH (1) /*!< No limitation to data bit width when using multiple slots */
/*-------------------------- ISP CAPS ----------------------------------------*/
#define SOC_ISP_NUMS 1U
#define SOC_ISP_AF_CTRLR_NUMS 1U
#define SOC_ISP_AF_ENV_DETECTOR_NUMS 1U
#define SOC_ISP_AF_WINDOW_NUMS 3
/*-------------------------- LEDC CAPS ---------------------------------------*/
#define SOC_LEDC_SUPPORT_PLL_DIV_CLOCK (1)
#define SOC_LEDC_SUPPORT_XTAL_CLOCK (1)